WO2022101870A1 - Manufacturing method of semiconductor electronic devices based on operations on a lead-frame - Google Patents
Manufacturing method of semiconductor electronic devices based on operations on a lead-frame Download PDFInfo
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- WO2022101870A1 WO2022101870A1 PCT/IB2021/060549 IB2021060549W WO2022101870A1 WO 2022101870 A1 WO2022101870 A1 WO 2022101870A1 IB 2021060549 W IB2021060549 W IB 2021060549W WO 2022101870 A1 WO2022101870 A1 WO 2022101870A1
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- lead frame
- test
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67282—Marking devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/98—Methods for disconnecting semiconductor or solid-state bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
Definitions
- the present invention relates to a production method of semiconductor devices , such as Integrated Circuits (IC or Integrated Circuit - IC ) , in particular to the phase Burn-in & Test to which such IC are subj ected to decree their compliance with design speci fications and the validity for the use in field, ensuring the necessary level of reliability over time .
- semiconductor devices such as Integrated Circuits (IC or Integrated Circuit - IC )
- phase Burn-in & Test to which such IC are subj ected to decree their compliance with design speci fications and the validity for the use in field, ensuring the necessary level of reliability over time .
- integrated circuits generally comprising an active semiconductor portion ( Chip ) connected to a plurality of electrical leads or pins ( Pin) to exchange electrical signals between the chip and the external electrical circuit , wherein the active portion is physically and electromagnetically protected by a cover (package ) typically obtained by a resin process (molding) with epoxy-based polymeric products .
- the leads ( Pin) are produced as part of a frame ( Lead Frame ) containing a support structure for the chip and a plurality of pins which will provide the electrical connection between the chip and the application circuit wherein the electronic device will be used .
- a single frame is able to accommodate more than one chip, arranged in a matrix, for a more ef ficient production process of electronic devices produced in series .
- a similar process is used for electronic devices with different contact configuration, such as those that instead of the pins have contact balls (Ball Grid Array)
- a single Lead Frame can contain a variable number of electronic devices, such as 35 devices, arranged in a 5-row and 7-column matrix.
- a known process of mass production of semiconductor devices comprises the steps of:
- Burn-in & Test Execution of a second test in the presence of thermal and electrical stress, e.g. Burn-in & Test, of each electronic device with relative rejection of the individual chips that do not pass the test.
- the Burn-in & Test process aims at eliminating devices with a low level of reliability by checking the basic functionality of the device and its behaviour in critical conditions .
- Final Test Execution of at least one final test, Final Test, for the total electronic functionality as defined by the sales technical specifications, at the end of which the chips that have passed the test are ready for sale, and can be used in the various applications relating to their functionality.
- the standard Burn-in & Test process is performed on singularized electronic devices, i.e. when the electronic device obtains the final physical configuration for its use, in particular in terms of separation from the frame and bending (forming) of the pins.
- the electronic devices that are found to be functional at the first test are inserted into slots ( sockets ) , suitable for the particular package of the electronic device to be processed, present in particular boards or housing j igs defined Burn- In Boards (BIB ) .
- the Burn-in boards (Burn- In-Boards ) have the task of electrically interconnecting the electronic devices , inserted in the sockets , with the stimulation and test electronics of the Burn-in & Test system .
- the Burn- in boards are therefore equipped with connectors ( di f ferent connection standards are used both finger and pins , by means of them the electrical connection is performed between the BIB, and therefore with the devices being tested inserted in the sockets , and the stimulation and test electronics of the Burn-in & Test system .
- All the pins of the sockets are connected via copper tracks present in the printed circuit ( PCB ) of the BIB to the connectors of the BIB itsel f .
- Some of these connections are independent ( typically the outputs of the electronic devices to be monitored) and others in parallel in such a way as to limit the number of fingers or contacts required between the BIB and the stimulation and test electronics of the Burn-in & Test system .
- the electronic module of the Burn-in & Test system that performs the stimulation and test functions is typically called the Driver board or Driver module .
- the Driver board provides the power supplies and the programmable stimulation signals to the electronic devices present in the BIB .
- the Driver board compares the outputs of the electronic devices with a programmable reference pattern to identi fy devices that are not working correctly . In fact , the non- compliance of the comparison of the output of the electronic device with the relative output pattern, programmed within the Driver board, highlights a mal function .
- the mal functioning devices and especially in short circuit can also damage the BIB and the Driver board .
- the purpose of the first test is to eliminate all non- functioning or critical electronic devices that could create excessive rej ected devices and also problems and damages during the Burn-in & Test process .
- BLU Battery-in Loader Unloader
- This device automatically inserts the singulari zed devices into the sockets of the BIBs . Therefore , at the BLU inlet there is a buf fer of empty BIBs and a buf fer of electronic devices , coming from the First Test , to be loaded on the BIBs .
- the BLU provides the BIB boards populated with the electronic devices that must be subj ected to the Burn-in & Test cycle .
- the BIB boards populated with the electronic devices are therefore manually inserted by the operators into the Burn-in & Test systems .
- the Burn-in & Test process is performed on electronic devices to eliminate infant mortality, guaranteeing a high level of quality and reliability .
- the level of reliability of electronic devices must be extremely high and at the moment the Burn-in & Test phase is the only process that guarantees the high level of reliability required .
- the electronic devices are therefore subj ected to functional tests under thermal and electrical stress conditions .
- the accelerating factors used for stress are the temperature (high, low or thermal cycling) and the supply voltage .
- the standard Burn-in & Test systems are typically composed of a thermal chamber wherein the BIB boards containing a plurality of already singular- i zed devices are inserted .
- the thermal chamber is programmed with the required stress temperature , typically high temperature ( typically in a range between + 150 and + 175 degrees Celsius ) but sometimes also low temperature ( typically in a range between - 10 and -50 degrees Celsius ) , where necessary .
- the Burn-in & Test system contains a certain number of Drivers boards , typically equal to the capacity of BIB that can be loaded into the system .
- the sequence of Burn-in & Test operations , temperature programming, test program execution, data analysis are performed by a controller and relative software program.
- the test program includes the sequence of stimulations , test patterns , test algo- rithms and rules for defining the correct functioning of the electronic devices . All the parameters related to the Burn-in & Test cycle are therefore programmable , e . g . temperature , power supplies , testing program and test , defining logics of the correct functioning of the electronic device .
- the data related to the tests performed are used to generate the final report through which the electronic devices that have failed or that have stopped working during the stress phase are identi fied .
- a map (BI Map ) is also generated which graphically represents the BIB board identi fying the position of the sockets with good devices on board and the position of the sockets that instead contain devices that have failed during the Burn-in & Test cycle .
- the final report is very detailed and provides useful information to identi fy necessary improvements to be performed to the chip to increase its performance and reliability . For example , the time , the stress temperature , the power supply value and the particular test performed at the time of the mal function of the electronic device are reported .
- the Burn-in & Test system not only allows to identi fy the defective devices to be eliminated from the production flow, guaranteeing the necessary level of reliability, but also to provide useful information to improve the functionality of the device and to increase its robustness and production performance .
- Integrated circuits rej ected during the Burn- in & Test cycle should be eliminated from the production cycle but are almost always subj ected to a second Burn-in & Test cycle .
- a second Burn-in & Test cycle is necessary to recover any devices erroneously rej ected due to problems not related to the device itsel f but mainly due to contact problems , typical of the standard Burn-in & Test on single devices .
- the BIB boards are manually unloaded from the Burn-in & Test system and transferred to the BLU .
- the BLU performs the opposite function (Unloader mode ) and automatically unloads the electronic devices from the BIBs , extracting them from the relative sockets .
- the BLU also performs the selection ( sorting) among the good devices and the rej ected ones in the Burn-in & Test cycle .
- the information on the status of the electronic device i . e .
- the Burn-in & Test system After the extraction of the devices from the sockets contained in the BIB and on the basis of the BI Map, performs the sorting and loads the working devices (Good devices) on one tray and the rejected devices (Bad devices) on another. It also positions the empty BIB boards in an output buffer, ready to be used for a new Burn-in & Test cycle.
- the rejected devices are often subjected to a second Burn-in & Test cycle in order to increase the final output.
- the second cycle of Burn-in & Test is used to eliminate erroneously rejected devices, for example because not correctly being positioned in the sockets of the BIBs, a problem not unusual especially when the device, which in the process just described is singularized, it has reduced dimensions and / or a high number of pins. Or due to the presence of a short-circuited device.
- the devices that have successfully passed the Burn-in & Test phase are sent to the final test (Final Test) to verify the compliance with the technical specification of use.
- the purpose of the present invention is therefore to solve at least to a large extent the above described problems by introducing a Burn-in & Test process of semiconductor devices on Lead Frame , with the obj ective of increasing the level of automation, productivity, ef ficiency of the process and at the same time reducing costs and times .
- a Lead Frame MAP is also created which will be updated at each subsequent process phase. This map will highlight, among other things, the position of the electronic devices that will be defined as failing in the various phases of the process;
- the Lead Frame is automatically positioned on a fixed contact platform, e.g. a bed of needles, so that all electronic devices on board the Lead Frame can be electrically connected to the testing system (tester) ;
- the identified Lead Frame code is read in such a way as to refer to the Lead Frame MAP;
- Performing a thermal cycle e . g . of Burn-in & Test on Lead Frame wherein the Lead Frame is subj ected to thermal and electrical stress while functional checks are performed on said plurality of semiconductor devices and during which the map of the electronic devices inside the Lead Frame is processed, classi fying each device according to the outcome of the tests ; in particular, the electrical tests performed on the electronic devices present in the Lead Frame during the thermal cycles are performed by means of a driver board belonging to the state of the art and, according to an aspect of the invention, the LF BIB ig electrically connects the chips of the Lead Frame to the driver board;
- At least two phases of the process downstream of the production phases of segmentation, connection and molding of the device are performed directly on the electronic components still positioned on the Lead Frame rather than on the singulari zed device .
- the above described phases of First Test and Burn-in with relative movements and, advantageously, removal of the mal functioning devices immediately after the detection thereof among the plurality of devices positioned on the frame are performed directly on the electronic components still positioned on the Lead Frame rather than on the singulari zed device .
- a signi ficant advantage of Burn-in & Test process on the Lead Frame is the high level of automation .
- the handling of the Lead Frame replaces that of the singularized devices or chips with evident advantages on productivity and reduction of transport and positioning times : by means of a single transport and positioning phase after molding all the transported chips are moved from the Lead Frame at the same time .
- a further important advantage is the elimination of a second cycle of Burn-in & Test .
- each chip / die that has not passed the test is eliminated from the Lead Frame .
- Flow A refers to the executive form wherein the Final Test is still performed on the Lead Frame .
- the advantage of handling the Lead Frame is exploited, including the Final Test phase .
- Flow B is exactly the same as Flow A but includes a further Trim & Form phase , performed by module A5 , with which passing from the Lead Frame to the single devices since the Final Test is performed at level of single devices .
- Flow A i s preferable because it extends the advantage of working on Lead Frame , rather than on single devices , even at the Final Test phase .
- the cutting and the formation of the leads of each electronic device are external to the process of the present invention, as it must necessarily be performed after the Final Test phase .
- Figure 1 illustrates as a whole a flow diagram of a new automatic Burn-in & Test process ( Flow A) for the production of chips according to the present invention, including schematic indications of the working areas assigned to each phase of such process .
- Figure 2 illustrates as a whole a flow diagram of a new automatic Burn-in & Test process ( Flow B ) for the production of semiconductor devices according to the present invention, including schematic indications of the working areas assigned to each phase of such process .
- a Lead Frame is produced in a known way where a plurality of chips are arranged, each comprising electrical leads , a semiconductor device electrically connected to the leads and encapsulated m a protective body . Furthermore, in the Lead Frame , each chip is still mechanically constrained to the frame so that a Lead Frame manipulator automatically transports all the chips constrained to it .
- a Lead Frame ready to be processed according to the invention has leads connected to electrically conductive tracks present on board the Lead Frame . In this way, each chip is constrained to the Lead Frame both through the leads ( conductors of electrical signals ) and through appendages of the frame itsel f .
- a Lead Frame as indicated above is operationally processed by a first module Al , called LF TESTER, to perform at least :
- each electronic device is still mechanically connected to the Frame .
- the Al module is configured to automatically perform, as a first operation, the writing of the Lead Frame identi fication code . In this way, all subsequent readings of the Lead Frame identi fication code , performed before each process phase , allow easy tracking of the Lead Frame and above all to perform the process phases correctly to each individual Lead Frame .
- module Al is structurally configured and also comprises a test system used to perform parametric tests and in particular :
- Short circuit ( Short circuit )
- the Lead Frame is automatically inserted into a needle contact fixture .
- This test fixture is connected to a Test system installed inside the LF TESTER .
- These electrical tests are particularly simple and their execution and equipment is relatively inexpensive , not bulky and easily integrated into the LF TESTER . As previously mentioned, these tests are extremely important to eliminate the defective devices that would create problems during the Burn-in & Test phase .
- the electronic devices are tested individually and separately in order to clearly identi fy any defective devices .
- each electronic device is connected independently from the others to the test fixture in such a way that each device is connected directly and uniquely to the test system;
- Module Al is also programmed to determine a spatial mapping of the chips on the Lead Frame (called Leda Frame MAP ) and assign the final result ( correlating it to the Lead Frame identi fication code ) , which takes into account all the parametric tests performed on each device of the Lead Frame ; and to command the conservation or elimination of a single device from the Lead Frame based on the test result and the Lead Frame MAP .
- the test system integrated in the LF TESTER is able to identi fy the device , e . g . the location of the device , which has failed one or more tests .
- a virtual map of the Lead Frame ( Lead Frame MAP ) is generated where the positions of the functioning and nonfunctioning devices are identi fied .
- the virtual map therefore includes the matrix position of the devices within the Lead Frame and classi fies the sta- tus of each one (working, not working) and, m executive variants of the invention, also other information for the classi fication of the single semiconductor unit (e . g . the electrical and / or cl imatic conditions wherein the breakage occurred, the time interval , voltage and / or current values detected on one or more leads , during which test within a series of tests the breakage occurred and result of the individual tests ) .
- the semiconductor device on board the Lead Frame that does not pass one or more tests is therefore removed from the Frame so that on the Lead Frame , at the module Al outlet , there are only electronic devices that have passed the testing phase of the First Test .
- the mechanical removal operation of the failing device is performed by module Al on the basis of the virtual map of the Lead Frame generated by the tester .
- the removal occurs for example by punching by means of a movable punch which selectively acts on the device at the position coordinates indicated by the virtual map .
- Figures 3 to 6 illustrate the detailed phases of each phase performed by the module Al named LF TESTER .
- LF TESTER the module Al
- T7 Automatically acquiring the Lead Frame identi fication code in order to update the Lead Frame MAP with the results of the test to be performed in the test station;
- T9 Automatically performing all the basic electrical tests ( Open, Short , Leakage and current measurement separately on each electronic device of the Lead Frame and advantageously in parallel in time i . e . more electronic devices are tested separately and simultaneously in the same time interval . Therefore , the test on electronic devices can performed in several steps or on all of them at the same time , speeding up the total test time required) and updating the Lead Frame MAP as well as generating the test report ;
- Ti l Automatically acquiring the Lead Frame identi fication code ;
- T12 Automatically removing the electronic devices from the Lead Frame that have not passed the tests previously performed . This operation is performed only in case of presence in the Lead Frame of electronic devices that have failed the test . In the absence of failing devices , the Lead Frame skips this process step . This operation is performed on the basis of the tests previously performed and referring to the LF MAP ;
- the Lead Frame processed by module Al is transferred autonomously to module A2 , named LF BL ( Lead Frame BIB Loading) to perform at least :
- the LF BIB contains a special contact fixture arranged for example with a bed of needles and relative alignment system .
- the Lead Frame is automatically inserted in the contact fixture which also comprises a particular cover which ensures the perfect locking of the Lead Frame inside the contact fixture and the perfect pressure between the Lead Frame and the needles of the contact fixture .
- the cover snaps onto the LF BIB mask and such closure is calibrated so that the cover applies a pre-determined pressure on the Lead Frame which ensures adequate contact between the pins and the bed of needles .
- a LF BIB can be configured to load even more Lead Frames and, for this purpose , the LF BIB which has its own identi fication code will be associated with the identi fication codes of all the Lead Frames present in the LF BIB, guaranteeing the complete traceability of each semiconductor device ;
- module A2 ( Lead Frame BIB Loader ) is configured to automatically perform, as a first operation, the reading o f the Lead Frame identi fication code .
- the identi fication code of the LF BIB board is also read .
- the Lead Frame is paired with the LF BIB board .
- the LF BL module performs the loading of the Lead Frame into the LF BIB board .
- the LF BLU module automatically picks a Lead Frame from the input Buf fer and an empty LF BIB board from the relative input Buf fer .
- the Lead Frame loading operation can be repeated several times in the event that a LF BIB is arranged to contain more Lead Frames .
- module A2 is structurally configured and also comprises a testing system used to perform parametric type tests and in particular :
- Short circuit ( Short circuit )
- the A2 module automatically makes the ready LF BIB available in an output buf fer for the Burn-in & Test process .
- the Al and A2 systems can be integrated to reali ze a single module between the stations of which the movement of the Lead Frame is operated for example by means of a belt conveyor or a shuttle .
- the advantage is to have a direct trans fer of Lead Frames from module Al to module A2 , remarkably improving the automation and reducing transport times from one module to another . Therefore , transfer activities between the two modules manually performed are eliminated .
- the spaces in the production area are also optimi zed .
- Figures 7 to 8 illustrate the detailed steps of each step performed by the module A2 , named LEAD FRAME BIB LOADER .
- LEAD FRAME BIB LOADER the module A2
- a BIB MAP mapping is generated whose structure allows to identi fy both the Lead Frame ( s ) carried by the LF BIB support and each electronic device of the corresponding Lead Frames so that , during the subsequent functionality test under thermal stress , the test result for each electronic device is uniquely associated both to the identi fication code of the Lead Frame and to that of the LF BIB support .
- the BIB MAP mapping keeps track of the arrangement of the Lead Frames and of the electronic devices on board the corresponding LF BIB support so that , based on the test result attributable to each electronic device, it is possible to recognize the relative Lead Frame on the basis of the position of the electronic device on board the LF BIB support .
- the electronic devices are therefore subj ected to functional tests under thermal and electrical stress conditions .
- the accelerating factors used for stress are in fact the temperature (high, low or thermal cycling) and the supply voltage .
- the known Standard Burn-in & Test systems used in this patent are typically composed of a thermal chamber wherein the BIB boards containing a plurality of already singulari zed devices are inserted .
- the thermal chamber is programmed with the required stress temperature .
- the Burn-in & Test system contains a certain number of Drivers boards typically equal to the BIB capacity that can be loaded into the system .
- the sequence of Burn-in & Test operations, temperature programming, test program execution, data analysis is performed by a controller and related software program.
- the test program includes the sequence of stimulations, test patterns, test algorithms and rules for defining the correct functioning of the electronic devices. All the parameters relating to the Burn-in & Test cycle are therefore programmable, e.g. temperature, power supplies, testing programs and tests, logic for defining the correct functioning of the electronic device.
- the driver boards exchange electrical stimulation and test signals and supply power to the Lead Frame (s) by means of the LF BIB jig.
- the final report generated by the Burn-in & Test system allows to identify the electronic devices that have failed or that have stopped working during the stress phase. Such result updates the BI MAP as well as the data relating to the Lead Frame MAP.
- LF BIB supports are brought back to module A4, this module is named LF BU (Lead Frame BIB Unloader) and the relative operational steps are represented in the Unloading mode.
- LF BU Lead Frame BIB Unloader
- the data of the Burn-In test are collected in an electronic map BIB-MAP associated with the support LF BIB, wherein more than one Lead Frame can be arranged.
- the identification code of the LF BIB support has been recognized, the related BIB MAP mapping is associated.
- Module A4 is structurally configured to automatically reading the code of the LF BIB, a fundamental operation before performing the extraction of the Lead Frame (or Lead Frames) from the LF BIB.
- the empty LF BIB is inserted in an output buffer. From this buffer the LF BIBs are picked to be used in another Burn-in cycle.
- the identification code of the Lead Frame is read to verify the presence of devices that have failed the tests during the Burn-in & Test cycle. If there are no rejected devices, LF BU module automatically positions the Lead Frame in the output Buffer.
- module A4 transfers the Lead Frame to the removal station of the failing device. After the step of removing the failing device, whose coordinates are provided by the BIB MAP mapping and the Lead Frame MAP mapping, the Lead Frame containing only good devices is positioned in the output buffer. It should be noted that the results of the Burn-In test collected in the BIB MAP mapping can be assigned to each Lead Frame and to the related LF MAP mapping by recogni zing the unique identi fication code of the Lead Frame ( s ) loaded on board the same support LF BIB .
- the related Lead Frame is recognized and thus the result of the Burn In test is also associated with the Lead Frame i . e . LF MAP mapping, as well as LF BIB support .
- the defective devices on board the Lead Frame are removed from the Lead Frame so that on this latter, at the A4 module output , there are Lead Frames containing only electronic devices that have passed the Burn-in & Test .
- the mechanical removal operation of the failing device is performed by the LF BU with the same methodology used in the Al system named LF TESTER .
- Figures 9 to 10 illustrate the detailed steps of each step performed by A4 LEAD FRAME BIB UNLOADER module .
- A4 LEAD FRAME BIB UNLOADER module illustrates the detailed steps of each step performed by A4 LEAD FRAME BIB UNLOADER module .
- the Lead Frames outgoing from module A4 will be sent directly to the Final Test .
- module A5 Trim & Form
- module A5 Trim & Form
- a Lead Frame is received wherein there are only devices that have passed all the tests and proceeds to the singulari zation step . Therefore , at the output of the A5 module there are individual electronic devices already tested and ready for the Final Test , in the assembly configuration, e . g . with pins conformed for connection to electronic boards etc .
- All or some of the steps and operations previ- ously described are performed by means of an electronic control comprising a calculation processor and a memory, the control system managing for example the text data, associating them to the LF MAP, BIB MAP mappings , receiving the data of the acqui- sition of the unique identi fication codes and providing commands for the removal of unsuitable electronic devices , transport , assembly on or disassembly from the LF BIB support etc .
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Abstract
The present invention refers to a new process method for the production of electronic semiconductor devices based on the execution of a greater number of production and test steps while the electronic devices are still carried by the Lead Frame.
Description
"Manufacturing method of semiconductor electronic devices based on operations on a lead-frame"
TEXT OF THE DESCRIPTION
TECHNICAL FIELD
The present invention relates to a production method of semiconductor devices , such as Integrated Circuits ( IC or Integrated Circuit - IC ) , in particular to the phase Burn-in & Test to which such IC are subj ected to decree their compliance with design speci fications and the validity for the use in field, ensuring the necessary level of reliability over time .
STATE OF ART
It is known to produce integrated circuits , generally comprising an active semiconductor portion ( Chip ) connected to a plurality of electrical leads or pins ( Pin) to exchange electrical signals between the chip and the external electrical circuit , wherein the active portion is physically and electromagnetically protected by a cover (package ) typically obtained by a resin process (molding) with epoxy-based polymeric products .
In the production phase , the leads ( Pin) are produced as part of a frame ( Lead Frame ) containing a support structure for the chip and a plurality of pins which will provide the electrical connection between the chip and the application circuit wherein the electronic device will be used . Commonly a single frame is able to accommodate more than one chip, arranged in a matrix, for a more ef ficient production process of electronic devices produced in series .
A similar process is used for electronic devices with different contact configuration, such as those that instead of the pins have contact balls (Ball Grid Array)
A single Lead Frame (frame) can contain a variable number of electronic devices, such as 35 devices, arranged in a 5-row and 7-column matrix.
A known process of mass production of semiconductor devices, either with pins package or with contact spheres (balls) , comprises the steps of:
- Segmentation of a portion of semiconductor material from a plate (Wafer) treated in advance for the realization of the electronic circuits in accordance with the design scheme of the device;
- Physical connection of the semiconductor device to the pins of the Lead Frame (e.g. according to the conductor wire connection technique known as Wire Bonding) ;
- Injection molding of a protective resin to provide the package for each single device present in the Lead Frame. After Molding operation, the Lead Frame is still to be considered in a semi-finished status i.e. further steps are still required to produce a device ready for sale;
- Separation from the Lead Frame of the individual devices individually packaged through a cutting or trimming operation;
- In the case of electronic devices with pins, forming e.g. bending of the pins of each sin- gularized device. At the end of the trimming &
forming operation, the device obtains its final configuration ready for its application use;
- Execution of a first preliminary verification test of the electronic functioning (First Test) generally aimed at identifying the non-functioning devices due to the production process with relative rejection of the individual ICs that do not pass the test.
- Execution of a second test in the presence of thermal and electrical stress, e.g. Burn-in & Test, of each electronic device with relative rejection of the individual chips that do not pass the test. The Burn-in & Test process aims at eliminating devices with a low level of reliability by checking the basic functionality of the device and its behaviour in critical conditions .
- Execution of at least one final test, Final Test, for the total electronic functionality as defined by the sales technical specifications, at the end of which the chips that have passed the test are ready for sale, and can be used in the various applications relating to their functionality.
In particular, the standard Burn-in & Test process is performed on singularized electronic devices, i.e. when the electronic device obtains the final physical configuration for its use, in particular in terms of separation from the frame and bending (forming) of the pins.
Therefore, at the inlet of the Burn-in & Test process there are the singularized ICs that have
passed the first test . The elimination of the devices found to be defective from the first test is necessary both to eliminate the devices that end up to be rej ected in relation to the preceding process phases and above all to prevent these rej ected devices from compromising the subsequent phases . Therefore it is necessary to eliminate all defective devices before starting the Burn-in & Test process . In fact , defective devices ( especially those in short circuit and with excessive current absorption) may cause mal functions and damages during the Burn- in & Test cycle , as it wi ll be speci fied in more detail below .
As part of the Burn-in & Test , the electronic devices that are found to be functional at the first test are inserted into slots ( sockets ) , suitable for the particular package of the electronic device to be processed, present in particular boards or housing j igs defined Burn- In Boards (BIB ) . The Burn-in boards (Burn- In-Boards ) have the task of electrically interconnecting the electronic devices , inserted in the sockets , with the stimulation and test electronics of the Burn-in & Test system . The Burn- in boards are therefore equipped with connectors ( di f ferent connection standards are used both finger and pins , by means of them the electrical connection is performed between the BIB, and therefore with the devices being tested inserted in the sockets , and the stimulation and test electronics of the Burn-in & Test system . All the pins of the sockets are connected via copper tracks present in the printed circuit ( PCB ) of the BIB to the connectors of the BIB itsel f . Some of these connections are independent
( typically the outputs of the electronic devices to be monitored) and others in parallel in such a way as to limit the number of fingers or contacts required between the BIB and the stimulation and test electronics of the Burn-in & Test system .
The electronic module of the Burn-in & Test system that performs the stimulation and test functions is typically called the Driver board or Driver module . As stimulation, the Driver board provides the power supplies and the programmable stimulation signals to the electronic devices present in the BIB . In the testing function, the Driver board compares the outputs of the electronic devices with a programmable reference pattern to identi fy devices that are not working correctly . In fact , the non- compliance of the comparison of the output of the electronic device with the relative output pattern, programmed within the Driver board, highlights a mal function . In order to increase the number of electronic devices to be processed in a BIB and therefore from the relative Driver board of a Burn- in & Test system, the technique of powering and piloting in parallel several electronic devices loaded in the sockets of the BIB board is used . On the one hand, this strategy increases the number of devices that can be powered and stimulated in parallel but on the other hand presents a serious criticality in the event that a short-circuited device or with excessive current absorption is present in the BIB board . In this case , all the electronic devices connected along the same power supply or stimulation line will not be piloted correctly and consequently could be erroneously rej ected during
the Burn-in & Test cycle . In some particular cases the mal functioning devices and especially in short circuit can also damage the BIB and the Driver board . For this reason, as anticipated, the purpose of the first test is to eliminate all non- functioning or critical electronic devices that could create excessive rej ected devices and also problems and damages during the Burn-in & Test process .
The operation of loading electronic devices into the sockets of the BIB is for example performed with an automatic device called BLU (Burn-in Loader Unloader ) . This device , during loading ( "Loader" mode ) , automatically inserts the singulari zed devices into the sockets of the BIBs . Therefore , at the BLU inlet there is a buf fer of empty BIBs and a buf fer of electronic devices , coming from the First Test , to be loaded on the BIBs .
As a result of the loading phase , the BLU provides the BIB boards populated with the electronic devices that must be subj ected to the Burn-in & Test cycle .
As part of the thermal and electrical stress phase , the BIB boards populated with the electronic devices are therefore manually inserted by the operators into the Burn-in & Test systems .
The Burn-in & Test process is performed on electronic devices to eliminate infant mortality, guaranteeing a high level of quality and reliability . For particular applications , such as the automotive , biomedical , military, aerospace sectors , the level of reliability of electronic devices must be extremely high and at the moment the Burn-in &
Test phase is the only process that guarantees the high level of reliability required .
During the Burn-in & Test cycle the electronic devices are therefore subj ected to functional tests under thermal and electrical stress conditions . In fact , the accelerating factors used for stress are the temperature (high, low or thermal cycling) and the supply voltage .
The standard Burn-in & Test systems are typically composed of a thermal chamber wherein the BIB boards containing a plurality of already singular- i zed devices are inserted . The thermal chamber is programmed with the required stress temperature , typically high temperature ( typically in a range between + 150 and + 175 degrees Celsius ) but sometimes also low temperature ( typically in a range between - 10 and -50 degrees Celsius ) , where necessary .
In the rear part of the thermal chamber there is a controlled room temperature area wherein the stimulation and test electronic modules are present ( Drivers boards or modules ) . Particular interconnection connectors provide the electrical connection between the Drivers boards and the BIB boards . Therefore , the Burn-in & Test system contains a certain number of Drivers boards , typically equal to the capacity of BIB that can be loaded into the system .
The sequence of Burn-in & Test operations , temperature programming, test program execution, data analysis are performed by a controller and relative software program. The test program includes the sequence of stimulations , test patterns , test algo-
rithms and rules for defining the correct functioning of the electronic devices . All the parameters related to the Burn-in & Test cycle are therefore programmable , e . g . temperature , power supplies , testing program and test , defining logics of the correct functioning of the electronic device .
At the end of the Burn-in & Test cycle , the data related to the tests performed are used to generate the final report through which the electronic devices that have failed or that have stopped working during the stress phase are identi fied .
A map (BI Map ) is also generated which graphically represents the BIB board identi fying the position of the sockets with good devices on board and the position of the sockets that instead contain devices that have failed during the Burn-in & Test cycle . The final report is very detailed and provides useful information to identi fy necessary improvements to be performed to the chip to increase its performance and reliability . For example , the time , the stress temperature , the power supply value and the particular test performed at the time of the mal function of the electronic device are reported . Therefore , the Burn-in & Test system not only allows to identi fy the defective devices to be eliminated from the production flow, guaranteeing the necessary level of reliability, but also to provide useful information to improve the functionality of the device and to increase its robustness and production performance .
Integrated circuits rej ected during the Burn- in & Test cycle should be eliminated from the production cycle but are almost always subj ected to a
second Burn-in & Test cycle . A second Burn-in & Test cycle is necessary to recover any devices erroneously rej ected due to problems not related to the device itsel f but mainly due to contact problems , typical of the standard Burn-in & Test on single devices . For example , incorrect insertion of the devices in the sockets , not perfect functioning of the sockets , bad contact between device and socket , bad contact between BIB and Driver board, presence of an electronic device in short circuit in the same group of devices connected between them in parallel , both to the power supply and to the stimulation signals , during the Burn-in & Test . This represents an important criticality of the current standard Burn-in & Test process performed on single devices from which a low output follows and very often the need to perform a second cycle of Burn-in & Test with additional times and costs .
At the end of the Burn-in & Test cycle , the BIB boards are manually unloaded from the Burn-in & Test system and transferred to the BLU . In this case the BLU performs the opposite function (Unloader mode ) and automatically unloads the electronic devices from the BIBs , extracting them from the relative sockets . In the unloading phase , the BLU also performs the selection ( sorting) among the good devices and the rej ected ones in the Burn-in & Test cycle . The information on the status of the electronic device , i . e . test passed or failed ( rej ected) , is provided by the Burn-in & Test system to BLU via the map (BI Map ) which identi fies the positions of the functioning and faulty devices in the BIB .
Therefore, the BLU system, after the extraction of the devices from the sockets contained in the BIB and on the basis of the BI Map, performs the sorting and loads the working devices (Good devices) on one tray and the rejected devices (Bad devices) on another. It also positions the empty BIB boards in an output buffer, ready to be used for a new Burn-in & Test cycle.
As previously said, the rejected devices are often subjected to a second Burn-in & Test cycle in order to increase the final output. The second cycle of Burn-in & Test is used to eliminate erroneously rejected devices, for example because not correctly being positioned in the sockets of the BIBs, a problem not unusual especially when the device, which in the process just described is singularized, it has reduced dimensions and / or a high number of pins. Or due to the presence of a short-circuited device. The devices that have successfully passed the Burn-in & Test phase are sent to the final test (Final Test) to verify the compliance with the technical specification of use.
It should be noted that many of the phases listed above are performed in respective and specific dedicated areas and specific handling devices are provided from one area to another. The standard validation process, including the Burn-in & Test phase, still contains various processes performed manually and there is no full automation of the process which introduces limits and complexity largely related to the characteristic of operating on singularized devices. In this context, the auto-
matic handling and manipulation of the single electronic devices is complicated and it is di f ficult to avoid the mixing among devices that have failed the tests and the devices that have passed the tests in the three phases identi fied and in particular in the first test and in the Burn-in & Test also as a consequence of the complicated traceability of the individual electronic devices within the process . PURPOSE AND SUMMARY OF THE INVENTION
The purpose of the present invention is therefore to solve at least to a large extent the above described problems by introducing a Burn-in & Test process of semiconductor devices on Lead Frame , with the obj ective of increasing the level of automation, productivity, ef ficiency of the process and at the same time reducing costs and times .
The purpose of the present invention is achieved by means of a Burn-in & Test process of integrated circuits on Lead Frame comprising as a whole the following phases , which can also be combined into sub-groups as indicated in the claims :
- Receiving a frame ( Lead Frame ) after an assembly phase (MOLDING) wherein a plurality of chips / die are arranged on said frame , electrically connected to a predetermined number of electrical leads being part of said frame , individually encapsulated in a protective housing e . g . of hot- formed polymeric resins ;
- Performing the marking of the Lead Frame automatically, for example by means of laser writing, in such a way as to match a unique identi fication code to each individual Lead Frame . In this phase , a Lead Frame MAP is also created which will be updated at
each subsequent process phase. This map will highlight, among other things, the position of the electronic devices that will be defined as failing in the various phases of the process;
- Advantageously but not exclusively, the Lead Frame is automatically positioned on a fixed contact platform, e.g. a bed of needles, so that all electronic devices on board the Lead Frame can be electrically connected to the testing system (tester) ;
- Automatically performing a first test on Lead Frame, after having contacted the Lead Frame with the tester. The purpose of this test is the identification of defective electronic devices positioned on the received frame, in particular those in short circuit or in a state of abnormal current absorption. In particular, in this test, the electronic devices are tested individually and separately in order to clearly identify any defective devices;
- Automatically updating the Lead Frame MAP as the final phase of the first test, highlighting the position of any failing devices;
- Automatically removing from the Frame, based on the result of the first test, all non-functioning electronic devices. It should be noted that before performing this operation, the identified Lead Frame code is read in such a way as to refer to the Lead Frame MAP;
Automatically loading (Loading) the Lead Frame in a dedicated board for the Burn-in & Test (LF BIB) , equipped with a contact feeler (fixture) to provide punctual electrical connections by contact with all the pins of the electronic devices present in the Lead Frame;
- Automatically reading the Lead Frame identi fication code and the LF BIB identi fication code , before performing the loading operations of the Lead Frame into the LF BIB . This operation allows to combine the single Lead Frame ( and possibly all the Lead Frames in the event that more Lead Frames will be loaded in the same LF BIB ) ensuring a total traceability and correlating the results of the Burn-in cycle both at the Lead Frame and at the LF BIB ;
- Automatically performing a test on the LF BIB ( PRETEST ) to ensure that the electrical connection of the Lead Frame with the contact fixture present in the LF BIB is good . This phase is important to avoid inserting LF BIB boards in the Burn-in & Test systems that could cause damages and delays in the cycle start-up phase ;
- Performing a thermal cycle e . g . of Burn-in & Test on Lead Frame , wherein the Lead Frame is subj ected to thermal and electrical stress while functional checks are performed on said plurality of semiconductor devices and during which the map of the electronic devices inside the Lead Frame is processed, classi fying each device according to the outcome of the tests ; in particular, the electrical tests performed on the electronic devices present in the Lead Frame during the thermal cycles are performed by means of a driver board belonging to the state of the art and, according to an aspect of the invention, the LF BIB ig electrically connects the chips of the Lead Frame to the driver board;
- Automatically unloading (Unloading) the Lead Frame from the LF BIB ( or possibly all the Lead Frames ) that has completed the Burn-in & Test cycle ;
- Automatically acquiring the identi fication code of the LF BIB j ig before performing the Lead Frame unloading operations . During the unloading phase , the Lead Frame identi fication code could also be read;
- Automatically selecting the electronic devices that have failed the Burn-in & Test cycle by processing the results of the tests performed ( First Test and Burn-in & Test ) , by means of an appropriate processing software program . This operation allows to identi fy the electronic devices to be eliminated from the single Lead Frame based on the information respectively present in the LF MAP, correlated to the identi fication code of the LF BIB and above all of the Lead Frame MAP, related to the Lead Frame identi fication code ;
- Automatically removing from the Lead Frame , on the basis of the result of the preceding processing, al l electronic devices that are not functioning;
According to the invention, at least two phases of the process downstream of the production phases of segmentation, connection and molding of the device are performed directly on the electronic components still positioned on the Lead Frame rather than on the singulari zed device . In particular, the above described phases of First Test and Burn-in with relative movements and, advantageously, removal of the mal functioning devices immediately after the detection thereof among the plurality of devices positioned on the frame .
A signi ficant advantage of Burn-in & Test process on the Lead Frame is the high level of automation . In this way, the handling of the Lead Frame
replaces that of the singularized devices or chips with evident advantages on productivity and reduction of transport and positioning times : by means of a single transport and positioning phase after molding all the transported chips are moved from the Lead Frame at the same time .
A further important advantage is the elimination of a second cycle of Burn-in & Test . In fact , at the end of the first test , performed on the LF TESTER, each chip / die that has not passed the test is eliminated from the Lead Frame . Furthermore , both because the contact of the Lead Frame on the LF BIB is performed with a needle fixture in a much more reliable way than the sockets and the presence of a PRETEST on the LF BIB, most of the contact criticalities , which require a second Burn-in & Test cycle to be performed, are eliminated . In fact , by means of a needle fixture , unlike what happens in singulari zed sockets , the alignment of the pins of the electronic devices with the contact solution is much more accurate and reliable , furthermore the pins of the chips are mechanical ly stressed in a much milder way and therefore the risk of high deformations which cause no contact in the sockets and even worse short circuits is considerably lower . Finally, the insertion mode of the individual electronic devices into the sockets damages the contact of the sockets pins in the long run .
It should not be underestimated another important advantage in processing electronic devices on Lead Frame related to an easier identi fication of the devices themselves in all the phases of the process , unlike the traditional process . In fact ,
to each Lead Frame is assigned a unique identi fication code and the single Lead Frame has an internal mapping ( e . g . rows and columns ) on the punctual position of each device in the Lead Frame itsel f .
Other advantages of the present invention are discussed in the description and cited in the dependent claims .
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described below on the basis of non-limiting examples illustrated by way of example in the following figures which illustrate :
- Fig . 1 a Flow A for the reali zation of electronic devices according to the present invention;
- Fig . 2 a Flow B for the reali zation of electronic devices according to the present invention;
- Figs . 3- 6 sub-phases performed by the operating module Al , named LF TESTER, to produce electronic devices according to a preferred embodiment of the present invention;
- Figs . 7- 8 sub-phases performed by the module A2 , named LF BL, to produce electronic devices according to a preferred embodiment of the present invention;
- Figs . 9- 10 sub-phases performed by the module A4 , named LF BU, to produce electronic devices according to a preferred embodiment of the present invention .
Flow A refers to the executive form wherein the Final Test is still performed on the Lead Frame . In this case , the advantage of handling the Lead Frame is exploited, including the Final Test phase .
Flow B is exactly the same as Flow A but includes a further Trim & Form phase , performed by module A5 , with which passing from the Lead Frame to the single devices since the Final Test is performed at level of single devices .
It should be noted that Flow A i s preferable because it extends the advantage of working on Lead Frame , rather than on single devices , even at the Final Test phase . In this embodiment , the cutting and the formation of the leads of each electronic device are external to the process of the present invention, as it must necessarily be performed after the Final Test phase .
On the contrary, in Flow B the Trim & Form phase is considered as an integrated phase within the Burn-in & Test process .
DETAILED DESCRIPTION OF THE INVENTION
Figure 1 illustrates as a whole a flow diagram of a new automatic Burn-in & Test process ( Flow A) for the production of chips according to the present invention, including schematic indications of the working areas assigned to each phase of such process .
Figure 2 illustrates as a whole a flow diagram of a new automatic Burn-in & Test process ( Flow B ) for the production of semiconductor devices according to the present invention, including schematic indications of the working areas assigned to each phase of such process .
According to the invention, a Lead Frame is produced in a known way where a plurality of chips are arranged, each comprising electrical leads , a semiconductor device electrically connected to the
leads and encapsulated m a protective body . Furthermore , in the Lead Frame , each chip is still mechanically constrained to the frame so that a Lead Frame manipulator automatically transports all the chips constrained to it . According to a preferred embodiment , a Lead Frame ready to be processed according to the invention has leads connected to electrically conductive tracks present on board the Lead Frame . In this way, each chip is constrained to the Lead Frame both through the leads ( conductors of electrical signals ) and through appendages of the frame itsel f .
A Lead Frame as indicated above is operationally processed by a first module Al , called LF TESTER, to perform at least :
- Writing an identi fication code on the Lead Frame . This operation is performed by means of a laser marking system ( Laser Marking) . Through this initial phase , the Lead Frame will be always identi fiable throughout the whole Burn-in & Test process ;
- Reading the Lead Frame identi fication code , in this way all the subsequent operations and related data will be always uniquely combined to the Lead Frame code . It should be highlighted that all the data relating to the Lead Frame , collected during all the process phases , including the Lead Frame MAP, will be always correlated with the Lead Frame identi fication code ;
- Blanking of the pins of the devices contained in the Lead Frame ( Pin Cutting) , for the purpose of electrical isolation of each device from the frame so that these latter can be connectable to equipment
to perform electrical tests on the semiconductor device . For example , the mechanical separation of the leads from the Lead Frame is performed by blanking with a cutting blade or sawing with a circular blade or punching . It should be noted that , after cutting the pins , each electronic device is still mechanically connected to the Frame .
- Electrical testing of Lead Frame electronic devices ( LF Testing) ;
- Removal of rej ected electronic devices , i . e . chips that do not pass the test ( Fail Device Removal ) . It should be remembered that the decision about which electronic device must be removed is determined on the basis of the Lead Frame MAP which identi fies the position of the good devices from those that have failed the First Test ;
According to a preferred embodiment of the invention, the Al module is configured to automatically perform, as a first operation, the writing of the Lead Frame identi fication code . In this way, all subsequent readings of the Lead Frame identi fication code , performed before each process phase , allow easy tracking of the Lead Frame and above all to perform the process phases correctly to each individual Lead Frame .
Preferably, module Al is structurally configured and also comprises a test system used to perform parametric tests and in particular :
- Short circuit ( Short circuit )
- Open circuit (Open)
- Current absorption ( Current consumption)
During the test phase , the Lead Frame is automatically inserted into a needle contact fixture . This
test fixture is connected to a Test system installed inside the LF TESTER . These electrical tests are particularly simple and their execution and equipment is relatively inexpensive , not bulky and easily integrated into the LF TESTER . As previously mentioned, these tests are extremely important to eliminate the defective devices that would create problems during the Burn-in & Test phase . In particular , in this test , the electronic devices are tested individually and separately in order to clearly identi fy any defective devices . In particular, each electronic device is connected independently from the others to the test fixture in such a way that each device is connected directly and uniquely to the test system;
Module Al is also programmed to determine a spatial mapping of the chips on the Lead Frame ( called Leda Frame MAP ) and assign the final result ( correlating it to the Lead Frame identi fication code ) , which takes into account all the parametric tests performed on each device of the Lead Frame ; and to command the conservation or elimination of a single device from the Lead Frame based on the test result and the Lead Frame MAP . In fact , the test system integrated in the LF TESTER is able to identi fy the device , e . g . the location of the device , which has failed one or more tests . A virtual map of the Lead Frame ( Lead Frame MAP ) is generated where the positions of the functioning and nonfunctioning devices are identi fied . The virtual map therefore includes the matrix position of the devices within the Lead Frame and classi fies the sta-
tus of each one (working, not working) and, m executive variants of the invention, also other information for the classi fication of the single semiconductor unit ( e . g . the electrical and / or cl imatic conditions wherein the breakage occurred, the time interval , voltage and / or current values detected on one or more leads , during which test within a series of tests the breakage occurred and result of the individual tests ) .
The semiconductor device on board the Lead Frame that does not pass one or more tests is therefore removed from the Frame so that on the Lead Frame , at the module Al outlet , there are only electronic devices that have passed the testing phase of the First Test . The mechanical removal operation of the failing device is performed by module Al on the basis of the virtual map of the Lead Frame generated by the tester . The removal occurs for example by punching by means of a movable punch which selectively acts on the device at the position coordinates indicated by the virtual map .
According to a preferred but non-limiting embodiment , Figures 3 to 6 illustrate the detailed phases of each phase performed by the module Al named LF TESTER . In particular :
T1 Managing the Lead Frame Input Buf fer for the Lead Frames coming from the MOLDING phase , as well as the automatic picking of the Lead Frame on which operating;
T2 Automatically applying a unique identi fication code on the Lead Frame e . g . by laser marking;
T3 Automatically moving the Lead Frame towards the cutting station of the pins of the electronic
devices present m the Lead Frame ( LF PINS CUTTING STATION) ;
T4 Automatically reading the Lead Frame identi fication code ;
T5 Automatically cutting the pins of all electronic devices included in the Lead Frame to allow the electrical tests ;
T 6 Automatically moving the Lead Frame towards the test station ( LF TEST STATION) ;
T7 Automatically acquiring the Lead Frame identi fication code in order to update the Lead Frame MAP with the results of the test to be performed in the test station;
T8 Automatically inserting the Lead Frame into the contact fixture of the test system e . g . the bed of needles ;
T9 Automatically performing all the basic electrical tests ( Open, Short , Leakage and current measurement separately on each electronic device of the Lead Frame and advantageously in parallel in time i . e . more electronic devices are tested separately and simultaneously in the same time interval . Therefore , the test on electronic devices can performed in several steps or on all of them at the same time , speeding up the total test time required) and updating the Lead Frame MAP as well as generating the test report ;
T10 Automatically disconnecting the Lead Frame from the contact fixture and automatically moving it to the FAIL DEVICE REMOVAL STATION;
Ti l Automatically acquiring the Lead Frame identi fication code ;
T12 Automatically removing the electronic devices from the Lead Frame that have not passed the tests previously performed . This operation is performed only in case of presence in the Lead Frame of electronic devices that have failed the test . In the absence of failing devices , the Lead Frame skips this process step . This operation is performed on the basis of the tests previously performed and referring to the LF MAP ;
T13 Automatically moving the Lead Frame in the Lead Frame Output Buf fer of module Al ;
The Lead Frame processed by module Al is transferred autonomously to module A2 , named LF BL ( Lead Frame BIB Loading) to perform at least :
- Reading of the Lead Frame identi fication code , in this way all the subsequent operations and related data will be always uniquely matched to the Lead Frame code ;
- Reading of the LF BIB identi fication code , in this way all subsequent operations and related data will be always uniquely matched to the LF BIB code ;
In Loading mode , performing the automatic loading of the Lead Frame on the LF BIB j ig . In particular, the LF BIB contains a special contact fixture arranged for example with a bed of needles and relative alignment system . The Lead Frame is automatically inserted in the contact fixture which also comprises a particular cover which ensures the perfect locking of the Lead Frame inside the contact fixture and the perfect pressure between the Lead Frame and the needles of the contact fixture . For example , the cover snaps onto the LF BIB mask and such closure is calibrated so that the cover applies
a pre-determined pressure on the Lead Frame which ensures adequate contact between the pins and the bed of needles . A LF BIB can be configured to load even more Lead Frames and, for this purpose , the LF BIB which has its own identi fication code will be associated with the identi fication codes of all the Lead Frames present in the LF BIB, guaranteeing the complete traceability of each semiconductor device ;
- In Loading mode, performing a test on the LF BIB to check the perfect contact of the Lead Frame i . e . of the individual semiconductor devices . Important purpose of the PRETEST is to eliminate possible problems that may create short circuits during the Burn-in & Test phase . This test is performed with a tester that performs tests similar to those of module Al ;
- Arranging at the output the LF BIBs containing the Lead Frame and which have passed the test ( PRETEST ) . These LF BIBs will be loaded into the Burn-in & Test systems to perform the Burn-in & Test process . Any LF BIB that has not passed the PRETEST is positioned in an output buf fer containing the rej ected LF BIBs during the test .
According to a preferred embodiment of the invention, module A2 , named LF BL, ( Lead Frame BIB Loader ) is configured to automatically perform, as a first operation, the reading o f the Lead Frame identi fication code . The identi fication code of the LF BIB board is also read . In this way, the Lead Frame is paired with the LF BIB board . As a subsequent operation ( Loading mode ) the LF BL module performs the loading of the Lead Frame into the LF BIB
board . During this step, the LF BLU module automatically picks a Lead Frame from the input Buf fer and an empty LF BIB board from the relative input Buf fer . Performs the insertion of the Lead Frame into the needle contact fixture taking advantage of the alignment and reference holes of the Lead Frame . Furthermore , it blocks the Lead Frame with a suitable cover to ensure the correct and stable contact between the pins of the Lead Frame and the fixture of the LF BIB board . The Lead Frame loading operation can be repeated several times in the event that a LF BIB is arranged to contain more Lead Frames .
Preferably, module A2 is structurally configured and also comprises a testing system used to perform parametric type tests and in particular :
- Short circuit ( Short circuit )
- Open circuit ( Open)
- Current absorption ( Current consumption)
After having automatically connected the LF BIB to the Tester, the tests j ust described are performed . These tests ( LF BIB PRETEST ) are particularly simple and their execution and equipment is relatively inexpensive , not bulky and easily integrable into the A2 module . These tests are extremely important to identi fy possible problems of bad contact and above all short circuits that would create problems during the Burn-in & Test phase . This type of problem is much reduced in the case of the Burn- in board configured to house the Lead Frame in any case a veri fication test allows to send to the Burn- in & Test process the LF BIB boards that do not have contact problems that could cause mal functions and
even damages during the Burn-in & Test cycle . The obj ective is to eliminate the re Burn-in .
At the end of the PRETEST , to complete the Loading mode , the A2 module automatically makes the ready LF BIB available in an output buf fer for the Burn-in & Test process . Note that the Al and A2 systems can be integrated to reali ze a single module between the stations of which the movement of the Lead Frame is operated for example by means of a belt conveyor or a shuttle . The advantage is to have a direct trans fer of Lead Frames from module Al to module A2 , remarkably improving the automation and reducing transport times from one module to another . Therefore , transfer activities between the two modules manually performed are eliminated . In addition, the spaces in the production area are also optimi zed .
According to a preferred but non-limiting embodiment , Figures 7 to 8 illustrate the detailed steps of each step performed by the module A2 , named LEAD FRAME BIB LOADER . In particular :
LI Automatic picking from the input Buf fer of the Lead Frames that have performed the First Test and that come from module Al of a single Lead Frame to automatically send it to the following station ( LF LOADING STATION) ;
L2 Automatic picking from the input Buf fer of the empty LF BIBs of a LF BIB to automatically send it to the next station ( LF LOADING STATION) ;
L3 Reading or automatic acquisition of the identi fication code of the LF BIB, this operation can be performed by reading a label present on the LF BIB with an optical reader ;
L4 Automatic reading or acquisition of the Lead Frame identi fication code ( operation repeated several times in the case of several Lead Frames inserted in the same LF BIB ) . It should be noted that , following these acquisitions , a BIB MAP mapping is generated whose structure allows to identi fy both the Lead Frame ( s ) carried by the LF BIB support and each electronic device of the corresponding Lead Frames so that , during the subsequent functionality test under thermal stress , the test result for each electronic device is uniquely associated both to the identi fication code of the Lead Frame and to that of the LF BIB support . For example , the BIB MAP mapping keeps track of the arrangement of the Lead Frames and of the electronic devices on board the corresponding LF BIB support so that , based on the test result attributable to each electronic device, it is possible to recogni ze the relative Lead Frame on the basis of the position of the electronic device on board the LF BIB support .
L5 Automatic operation of inserting the Lead Frame in the contact fixture of the LF BIB . This operation will be repeated several times in the case of more Lead Frames to be loaded in the same LF BIB ;
L6 Automatic handling of the LF BIB to the following station ( LF BIB PRETEST STATION) e . g . by means of a conveyor belt ;
L7 Automatic insertion of the contact connector of the testing system/board into the finger contacts of the LF BIB ;
L8 Automatic reading of the identi fication code , e . g . an electrical code , of the Lead Frame by means of the fingers of the LF BIB and subsequent
execution of the tests . The purpose of this speci fic test , named PRETEST , is to identi fy possible anomalies in the contact between the Lead Frame ( s ) and the contact fixture of the LF BIB ;
L9 Automatic handling of the LF BIB that has not passed the test in an output Buf fer containing the defective LF BIBs in order to be analysed;
LI O Automatic handling of the LF BIB that has passed the test in the output Buf fer of the LF BIBs ready to be sent to the Burn-in & Test cycle .
During the Standard Burn-in & Test cycle , represented with the A3 module , the electronic devices are therefore subj ected to functional tests under thermal and electrical stress conditions . The accelerating factors used for stress are in fact the temperature (high, low or thermal cycling) and the supply voltage .
The known Standard Burn-in & Test systems used in this patent are typically composed of a thermal chamber wherein the BIB boards containing a plurality of already singulari zed devices are inserted . The thermal chamber is programmed with the required stress temperature .
In the rear part of the thermal chamber there is a controlled room temperature area wherein the stimulation and testing electronic modules (boards or Drivers modules ) are present . Particular interconnection connectors provide the electrical connection between the Drivers boards and the BIB boards . Therefore , the Burn-in & Test system contains a certain number of Drivers boards typically equal to the BIB capacity that can be loaded into the system .
The sequence of Burn-in & Test operations, temperature programming, test program execution, data analysis is performed by a controller and related software program. The test program includes the sequence of stimulations, test patterns, test algorithms and rules for defining the correct functioning of the electronic devices. All the parameters relating to the Burn-in & Test cycle are therefore programmable, e.g. temperature, power supplies, testing programs and tests, logic for defining the correct functioning of the electronic device. The driver boards exchange electrical stimulation and test signals and supply power to the Lead Frame (s) by means of the LF BIB jig.
The final report generated by the Burn-in & Test system allows to identify the electronic devices that have failed or that have stopped working during the stress phase. Such result updates the BI MAP as well as the data relating to the Lead Frame MAP.
At the end of the Burn-in & Test cycle, the LF BIB supports are brought back to module A4, this module is named LF BU (Lead Frame BIB Unloader) and the relative operational steps are represented in the Unloading mode. In particular:
- Receiving the LF BIB that performed the Burn- in & Test cycle at the Buffer input:
- Reading of the identification code of the LF BIB before performing the step of unloading the Lead Frame from the LF BIB;
- Extracting the Lead Frame from the contact fixture of the LF BIB. At the same time, reading the Lead Frame identification code;
- Removing the rejected device, i.e. chips that have not passed the Burn-in & Test cycle (Fail Device Removal) .
Preferably, the data of the Burn-In test are collected in an electronic map BIB-MAP associated with the support LF BIB, wherein more than one Lead Frame can be arranged. Once the identification code of the LF BIB support has been recognized, the related BIB MAP mapping is associated.
Module A4 is structurally configured to automatically reading the code of the LF BIB, a fundamental operation before performing the extraction of the Lead Frame (or Lead Frames) from the LF BIB. The empty LF BIB is inserted in an output buffer. From this buffer the LF BIBs are picked to be used in another Burn-in cycle. After the step of extraction of the Lead Frame from the LF BIB, the identification code of the Lead Frame is read to verify the presence of devices that have failed the tests during the Burn-in & Test cycle. If there are no rejected devices, LF BU module automatically positions the Lead Frame in the output Buffer. If, on the other hand, one or more rejected devices may result from the data relating to the BIB MAP coming from the Burn-in module A3, module A4 transfers the Lead Frame to the removal station of the failing device. After the step of removing the failing device, whose coordinates are provided by the BIB MAP mapping and the Lead Frame MAP mapping, the Lead Frame containing only good devices is positioned in the output buffer. It should be noted that the results of the Burn-In test collected in the BIB MAP mapping can be assigned to each Lead Frame and to
the related LF MAP mapping by recogni zing the unique identi fication code of the Lead Frame ( s ) loaded on board the same support LF BIB . For example , based on the position of an electronic device on board the LF BIB support , the related Lead Frame is recogni zed and thus the result of the Burn In test is also associated with the Lead Frame i . e . LF MAP mapping, as well as LF BIB support .
Also for the LF BU system the defective devices on board the Lead Frame are removed from the Lead Frame so that on this latter, at the A4 module output , there are Lead Frames containing only electronic devices that have passed the Burn-in & Test . The mechanical removal operation of the failing device is performed by the LF BU with the same methodology used in the Al system named LF TESTER .
According to a preferred but non-limiting embodiment , Figures 9 to 10 illustrate the detailed steps of each step performed by A4 LEAD FRAME BIB UNLOADER module . In particular
U1 Automatic picking from the input Buf fer of the LF BIBs that have performed the Burn-in & Test cycle of an LF BIB and automatical ly send it to the next station ( LF UNLOADING STATION) ;
U2 Automatic reading of the identification code e . g . optical identi fication of a non-electrical identi fication code of the LF BIB ;
U3 Automatic operation of extraction of the Lead Frame in the contact fixture of the LF BIB . This operation will be repeated several times in the case of more Lead Frames present in the same LF BIB ;
U4 Automatic handling of the Lead Frame to the following station ( FAIL REMOVAL STATION) . In parallel , the LF BIB emptied from the Lead Frame , or from the Lead Frames , will be automatically inserted in the output Buf fer of the empty LF BIBs ;
U5 Automatic reading of the Lead Frame identification code to automatically access the data relating to this Lead Frame , in particular the LF MAP data .
U6 Automatic removal from the Lead Frame of electronic devices that have not passed the tests of the Burn-in & Test cycle . This operation is performed only in the presence of electronic devices in the Lead Frame that have failed the test . In the absence of failing devices , the Lead Frame skips this process phase ;
U7 Automatic handling of the Lead Frame in the output Buf fer relating to the Lead Frames that will be sent to the Final Test in the case of Flow A. In the case of Flow B these Lead Frames will be sent to module A5 .
In the case of Flow A, the Lead Frames outgoing from module A4 will be sent directly to the Final Test . In the case of Flow B they will be sent to module A5 ( Trim & Form) , which is part of Flow B, to perform the singulari zation step of the electronic devices present in the Lead Frame . With reference to module A5 , a Lead Frame is received wherein there are only devices that have passed all the tests and proceeds to the singulari zation step . Therefore , at the output of the A5 module there are individual electronic devices already tested and
ready for the Final Test , in the assembly configuration, e . g . with pins conformed for connection to electronic boards etc .
In the case of Flow A we have the Lead Frames at the output with the electronic devices that have passed the Burn-in & Test cycle ready to be subj ected to the Final Test , equipped to directly test electronic devices still present in the Lead Frame .
All or some of the steps and operations previ- ously described are performed by means of an electronic control comprising a calculation processor and a memory, the control system managing for example the text data, associating them to the LF MAP, BIB MAP mappings , receiving the data of the acqui- sition of the unique identi fication codes and providing commands for the removal of unsuitable electronic devices , transport , assembly on or disassembly from the LF BIB support etc .
Claims
1. Method for producing electronic devices on Lead Frame comprising the steps of:
Receiving (Tl) a Lead Frame after a molding step (MOLDING) wherein a plurality of said electronic devices are protected by a resin on the respective electrically conductive tracks connected to the related pins;
Performing a standard thermal cycle (A3) e.g. of Burn-in & Test on Lead Frame
Performing at least one of the following steps :
0 Before performing the thermal cycle, performing a first test (T9 - FIRST TEST) of electrical functionality on the electronic devices;
0 During the thermal cycle (A3) , performing a second electrical functionality test on the electronic devices under stress;
After at least one of the first and second electrical functionality tests:
0 recording (LF MAP) the result of said at least one test; and
0 deciding whether to remove (T12; U6) one or more electronic devices from the Lead Frame based on said result.
2. Method according to claim 1, comprising the step of applying (L5) the Lead Frame on a support (LF BIB) which provides both the electrical contact between the electronic devices of the Lead Frame and the connection with a stimulation and test electronics programmed to perform said second test.
3. Method according to claim 2, wherein between the step of applying (L5) and the step of performing
the Burn-in & Test cycle (A3) a further test step (L8) is provided, defined as PRETEST, necessary to check the electrical contacts between the Lead Frame and an electrical contact fixture of said support (LF BIB) .
4. Method according to one of claims 2 or 3, wherein said support (LF BIB) is configured to comprise a first bed of needles to achieve said electrical contact with the electronic devices of the Lead Frame.
5. Method according to any one of the preceding claims, comprising the step of recognizing (T4; T7; Til; L4; U5) a first unique identification code of a Lead Frame and by the fact that said step of recording associates the result with the identification code.
6. Method according to claims 4 and 5, wherein said support (LF BIB) is associated with a second unique identification code and by the fact of comprising the step of associating said first and second identification codes (L3, U2) .
7. Method according to any one of the preceding claims, wherein said recording step comprises a step of recording in a mapping associated with each Lead Frame, comprising for each electronic device of the Lead Frame, an information of status comprising at least one datum relating to the test result and a datum relating to the presence on board the Lead Frame .
8. Method according to any one of the preceding claims, wherein the step of performing the first electrical functionality test comprises the step of applying the Lead Frame on a needle contact fixture
configured to electrically connect each electronic device to an electronic module in order to perform the electrical functionality test and wherein said electrical functionality test comprises, independently for each electronic device, at least one among short circuit test, open circuit test and current absorption test.
9. Method according to claim 8, comprising a step of cutting (T5) the pins of the electronic devices preceding said step of applying (T8) the Lead Frame on a contact fixture.
10. Method according to claim 9, comprising the step of bending the pins following said step of performing a thermal cycle.
11. Method for producing electronic devices on Lead Frame comprising the steps of:
Receiving (Tl) a Lead Frame after a molding step (MOLDING) wherein a plurality of said electronic devices are protected by a resin on the respective electrically conductive tracks connected to the related pins;
Performing a first (T9 - FIRST TEST) electrical functionality test by automatically connecting (T8) each electronic device separately and independently from the others to the contact fixture of a test system to obtain a result for each electronic device;
Recording (LF MAP) the result of said test; and
Deciding whether to remove (T12) one or more electronic devices from the Lead Frame on the basis of said result.
12. Method according to claim 11, comprising the step of recognizing (T4) a first unique identification code of a Lead Frame and by the fact that said recording step associates the result with the identification code.
13. Method according to claim 12, comprising the step of applying (T2) said identification code to the Lead Frame.
14. Method according to any one of claims from 11 to 13, comprising a step of cutting (T5) the pins of the electronic devices preceding said step of performing the first test and after said step of receiving ( T1 ) .
15. Method according to any one of claims from 11 to 14, wherein said step of performing a first test comprises the step of applying the Lead Frame on a bed of needles contact device (T8) electrically connected to said electronic board.
16. Method according to any one of the preceding claims, further comprising the step of performing a thermal cycle (A3) e.g. of Burn-in on the Lead Frame .
17. Method according to claim 16, comprising the step of applying (L5) the Lead Frame on a support (LF BIB) which provides both the electrical contact between the electronic devices of the Lead Frame and the connection with a stimulation and test electronics programmed to perform a second electrical function test during said thermal cycle.
18. Method according to claim 17, wherein said support (LF BIB) is configured to comprise a second bed of needles to achieve said electrical contact.
19. Method according to claims 17 or 18, wherein said support (LF BIB) is associated with a second unique identification code and by the fact of comprising the step of associating said first and second identification codes (L3, L4) so that, on the basis of a test result associated with one of said electronic devices on the support (LF BIB) , it is possible to recognize the Lead Frame of the electronic device and the corresponding LF MAP mapping.
20. Method according to any one of the preceding claims, wherein said recording step comprises a step of recording in a mapping associated with each Lead Frame, comprising for each electronic device of the Lead Frame, an information of status comprising at least one datum relating to the test result and a datum relating to the presence on board the Lead Frame.
21. Method for producing electronic devices on Lead Frame comprising the steps of:
Receiving (LI) a Lead Frame having electronic devices subjected to a previous test on the electrical and / or electronic functionalities;
Assembling (L5) the Lead Frame on a support (LF BIB) configured to provide both an electrical contact between the electronic devices of the Lead Frame and a connection with a stimulation and test electronics programmed to perform a second test of electrical functionality during a thermal cycle applied to the Lead Frame.
22. Method according to claim 21, further comprising the step of performing a first test (L8) to check the electrical contacts between the electronic
devices of the Lead Frame and the electrical contact of said support (LF BIB) .
23. Method according to one of claims 21 or 22, comprising the step of acquiring a mapping (LF MAP) associated with each Lead Frame, comprising for each electronic device of the Lead Frame, a status information comprising at least one datum relating to the outcome of the previous test and a data relating to the presence on board the Lead Frame.
24. Method according to claim 23, comprising the step of recognizing (L4) a first unique identification code of the Lead Frame and the step of acquiring said mapping (LF MAP) on the basis of said first unique identification code.
25. Method according to claim 24, wherein said support (LF BIB) is associated with a second unique identification code (L3) and by comprising the step of associating said first and second identification codes so that, on the basis of a test result associated with one of said electronic devices on the support (LF BIB) , it is possible to recognize the Lead Frame of the electronic device and the corresponding LF MAP mapping.
26. Method according to claims from 22 to 25, wherein said step of performing the first test (L8) is preceded by a step of acquiring said second identification code.
27. Method according to any one of the preceding claims, wherein said support (LF BIB) is configured to comprise a bed of needles to provide said electrical contact.
28. Method according to any one of the preceding claims, further comprising the steps of:
- Applying (A3) a thermal stress to the Lead Frame while the support (LF BIB) is electrically connected to said electronic board to perform at least one further test (Burn-In) on the electronic devices ;
- Recording (LF MAP) the result of said further test; And
- Deciding whether to remove (U6) one or more electronic devices from the Lead Frame on the basis of said result.
29. Method for producing electronic devices on Lead Frame comprising the steps of:
- Receiving (Ul) a support (LF BIB) with a Lead Frame having electronic devices subjected to a preceding test on the electrical and / or electronic functionalities, said support (LF BIB) being configured to provide both an electrical contact between the electronic devices of the Lead Frame and a connection with a stimulation and test electronics programmed to perform a second electrical functionality test during a thermal cycle applied to the Lead Frame;
- Disassembling (U3) the Lead Frame from said support (LF BIB) .
30. Method according to claim 29, wherein said support (LF BIB) is associated with a first unique identification code (U2) and from the step of acquiring a first mapping (BIB MAP) on the basis of said first code univocal identifier, the said mapping (BIB MAP) comprising status information of the electronic devices carried by the said support LF BIB.
31. Method according to claim 30, comprising the step of acquiring (U5) a second unique code (U5) of one of the Lead Frames carried by said support (LF BIB) and of acquiring, starting from said first mapping (BIB MAP) , a second mapping (LF MAP) comprising status information on the Lead Frame identified by said second unique code, wherein said second mapping (LF MAP) comprises for each electronic device of the Lead Frame, a status information comprising at least one datum relating to the result of the previous test and a datum relating to the presence on board the Lead Frame and wherein, on the basis of a test result associated with one of said electronic devices on the support (LF BIB) , it is possible to recognize the Lead Frame of the electronic device and the corresponding LF BIB mapping.
32. Method according to any one of claims from 30 to 31, further comprising the step of deciding whether to remove (U6) one or more electronic devices from the Lead Frame on the basis of said result .
33. Method according to any of the claims from 29 to 32, wherein the said support (LF BIB) is configured to comprise a bed of needles to provide said electrical contact.
34. Method according to any one of claims 29 to 33, comprising the step of bending the pins of the electrical devices following said step of disassembling (U3) .
35. Method according to any one of claims from 29 to 34, further comprising, preceding said step of receiving (Ul) , the steps of:
- Applying (A3) a thermal stress to the Lead Frame while the support (LF BIB) is electrically connected to said electronic board to perform at least one further test on the electronic devices; And
- Recording (LF MAP; BIB MAP) the result of said further test.
42
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102020000027254 | 2020-11-13 | ||
| IT102020000027269 | 2020-11-13 | ||
| IT102020000027281 | 2020-11-13 | ||
| IT202000027281 | 2020-11-13 | ||
| IT102020000027224 | 2020-11-13 | ||
| IT202000027224 | 2020-11-13 | ||
| IT202000027269 | 2020-11-13 | ||
| IT202000027254 | 2020-11-13 |
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| Publication Number | Publication Date |
|---|---|
| WO2022101870A1 true WO2022101870A1 (en) | 2022-05-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2021/060549 WO2022101870A1 (en) | 2020-11-13 | 2021-11-15 | Manufacturing method of semiconductor electronic devices based on operations on a lead-frame |
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| Country | Link |
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| WO (1) | WO2022101870A1 (en) |
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| US5557559A (en) * | 1992-07-06 | 1996-09-17 | Motay Electronics, Inc. | Universal burn-in driver system and method therefor |
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| GB2148865A (en) * | 1983-10-26 | 1985-06-05 | Reliability Inc | Automated burn-in board unloader and IC package sorter |
| US4584764A (en) * | 1983-10-26 | 1986-04-29 | Reliability Incorporated | Automated burn-in board unloader and IC package sorter |
| US4855672A (en) * | 1987-05-18 | 1989-08-08 | Shreeve Robert W | Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same |
| US5557559A (en) * | 1992-07-06 | 1996-09-17 | Motay Electronics, Inc. | Universal burn-in driver system and method therefor |
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