DE69233231D1 - Verfahren zur Herstellung von Kontaktbohrungen für Mehrschichtschaltung von Halbleiterbauelementen - Google Patents

Verfahren zur Herstellung von Kontaktbohrungen für Mehrschichtschaltung von Halbleiterbauelementen

Info

Publication number
DE69233231D1
DE69233231D1 DE69233231T DE69233231T DE69233231D1 DE 69233231 D1 DE69233231 D1 DE 69233231D1 DE 69233231 T DE69233231 T DE 69233231T DE 69233231 T DE69233231 T DE 69233231T DE 69233231 D1 DE69233231 D1 DE 69233231D1
Authority
DE
Germany
Prior art keywords
production
semiconductor components
multilayer switching
contact bores
bores
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69233231T
Other languages
English (en)
Other versions
DE69233231T2 (de
Inventor
Masako Iizuka
Ryoichi Mukai
Motoo Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69233231D1 publication Critical patent/DE69233231D1/de
Application granted granted Critical
Publication of DE69233231T2 publication Critical patent/DE69233231T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69233231T 1991-01-28 1992-01-27 Verfahren zur Herstellung von Kontaktbohrungen für Mehrschichtschaltung von Halbleiterbauelementen Expired - Fee Related DE69233231T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP846491 1991-01-28
JP846491 1991-01-28

Publications (2)

Publication Number Publication Date
DE69233231D1 true DE69233231D1 (de) 2003-11-20
DE69233231T2 DE69233231T2 (de) 2004-08-12

Family

ID=11693859

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69233231T Expired - Fee Related DE69233231T2 (de) 1991-01-28 1992-01-27 Verfahren zur Herstellung von Kontaktbohrungen für Mehrschichtschaltung von Halbleiterbauelementen

Country Status (5)

Country Link
US (1) US5250465A (de)
EP (1) EP0498550B1 (de)
JP (1) JPH05304149A (de)
KR (1) KR960002059B1 (de)
DE (1) DE69233231T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0608628A3 (de) * 1992-12-25 1995-01-18 Kawasaki Steel Co Verfahren zur Herstellung einer Halbleitervorrichtung mit Mehrlagen-Verbindungsstruktur.
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
JP2882572B2 (ja) * 1994-08-31 1999-04-12 インターナショナル・ビジネス・マシーンズ・コーポレイション 金属薄膜をレーザで平坦化する方法
KR100336554B1 (ko) * 1994-11-23 2002-11-23 주식회사 하이닉스반도체 반도체소자의배선층형성방법
KR0179827B1 (ko) * 1995-05-27 1999-04-15 문정환 반도체 소자의 배선 형성방법
US6077781A (en) * 1995-11-21 2000-06-20 Applied Materials, Inc. Single step process for blanket-selective CVD aluminum deposition
US5877087A (en) 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US6726776B1 (en) 1995-11-21 2004-04-27 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
JPH1064902A (ja) * 1996-07-12 1998-03-06 Applied Materials Inc アルミニウム材料の成膜方法及び成膜装置
US6001420A (en) * 1996-09-23 1999-12-14 Applied Materials, Inc. Semi-selective chemical vapor deposition
KR100423065B1 (ko) * 1996-12-28 2004-06-10 주식회사 하이닉스반도체 반도체소자의키-홀발생방지방법
US6537905B1 (en) 1996-12-30 2003-03-25 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6139697A (en) * 1997-01-31 2000-10-31 Applied Materials, Inc. Low temperature integrated via and trench fill process and apparatus
US5989623A (en) 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization
US6605531B1 (en) 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US7202497B2 (en) * 1997-11-27 2007-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4014710B2 (ja) 1997-11-28 2007-11-28 株式会社半導体エネルギー研究所 液晶表示装置
JPH11186194A (ja) * 1997-12-19 1999-07-09 Nec Corp 半導体装置の製造方法
US6057236A (en) * 1998-06-26 2000-05-02 International Business Machines Corporation CVD/PVD method of filling structures using discontinuous CVD AL liner
US6207558B1 (en) 1999-10-21 2001-03-27 Applied Materials, Inc. Barrier applications for aluminum planarization
FR2801814B1 (fr) * 1999-12-06 2002-04-19 Cebal Procede de depot d'un revetement sur la surface interne des boitiers distributeurs aerosols
US6797620B2 (en) * 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
US7687917B2 (en) * 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
US6716733B2 (en) * 2002-06-11 2004-04-06 Applied Materials, Inc. CVD-PVD deposition process
JP4202091B2 (ja) * 2002-11-05 2008-12-24 株式会社半導体エネルギー研究所 アクティブマトリクス型液晶表示装置の作製方法
US7384862B2 (en) 2003-06-30 2008-06-10 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating semiconductor device and display device
KR102262292B1 (ko) * 2018-10-04 2021-06-08 (주)알엔알랩 반도체 디바이스 제조 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933850A (ja) * 1982-08-19 1984-02-23 Toshiba Corp 半導体装置の製造方法
JPS5961146A (ja) * 1982-09-30 1984-04-07 Toshiba Corp 半導体装置の製造方法
DE3685449D1 (de) * 1985-03-15 1992-07-02 Fairchild Semiconductor Corp., Cupertino, Calif., Us
JPH0691087B2 (ja) * 1986-07-31 1994-11-14 富士通株式会社 半導体装置の製造方法
JPS6344739A (ja) * 1986-08-12 1988-02-25 Fujitsu Ltd 半導体装置の製造方法
JPH0691159B2 (ja) * 1986-08-19 1994-11-14 富士通株式会社 半導体装置の製造方法
US4826785A (en) * 1987-01-27 1989-05-02 Inmos Corporation Metallic fuse with optically absorptive layer
JPH01287949A (ja) * 1988-05-13 1989-11-20 Seiko Epson Corp 半導体装置の製造方法
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
JPH0666287B2 (ja) * 1988-07-25 1994-08-24 富士通株式会社 半導体装置の製造方法
US5110759A (en) * 1988-12-20 1992-05-05 Fujitsu Limited Conductive plug forming method using laser planarization
EP0388563B1 (de) * 1989-03-24 1994-12-14 STMicroelectronics, Inc. Verfahren zum Herstellen eines Kontaktes/VIA
US4970176A (en) * 1989-09-29 1990-11-13 Motorola, Inc. Multiple step metallization process
US5032233A (en) * 1990-09-05 1991-07-16 Micron Technology, Inc. Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization

Also Published As

Publication number Publication date
KR960002059B1 (ko) 1996-02-10
EP0498550A1 (de) 1992-08-12
US5250465A (en) 1993-10-05
JPH05304149A (ja) 1993-11-16
DE69233231T2 (de) 2004-08-12
EP0498550B1 (de) 2003-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee