DE69224270T2 - Speicher mit Generator zum Folgen eines Vorladungsimpulses - Google Patents

Speicher mit Generator zum Folgen eines Vorladungsimpulses

Info

Publication number
DE69224270T2
DE69224270T2 DE69224270T DE69224270T DE69224270T2 DE 69224270 T2 DE69224270 T2 DE 69224270T2 DE 69224270 T DE69224270 T DE 69224270T DE 69224270 T DE69224270 T DE 69224270T DE 69224270 T2 DE69224270 T2 DE 69224270T2
Authority
DE
Germany
Prior art keywords
generator
memory
following
charge pulse
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224270T
Other languages
English (en)
Other versions
DE69224270D1 (de
Inventor
Ryuji Yonemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69224270D1 publication Critical patent/DE69224270D1/de
Publication of DE69224270T2 publication Critical patent/DE69224270T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
DE69224270T 1991-11-20 1992-11-11 Speicher mit Generator zum Folgen eines Vorladungsimpulses Expired - Fee Related DE69224270T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/795,103 US5386150A (en) 1991-11-20 1991-11-20 Tracking pulse generator and RAM with tracking precharge pulse generator

Publications (2)

Publication Number Publication Date
DE69224270D1 DE69224270D1 (de) 1998-03-05
DE69224270T2 true DE69224270T2 (de) 1998-05-14

Family

ID=25164676

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224270T Expired - Fee Related DE69224270T2 (de) 1991-11-20 1992-11-11 Speicher mit Generator zum Folgen eines Vorladungsimpulses

Country Status (5)

Country Link
US (1) US5386150A (de)
EP (1) EP0543269B1 (de)
JP (1) JPH05210983A (de)
KR (1) KR970000362B1 (de)
DE (1) DE69224270T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10128757A1 (de) * 2001-06-13 2003-01-02 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Regeln der Betriebsspannung einer Digitalschaltung

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JP3130705B2 (ja) * 1993-06-25 2001-01-31 株式会社東芝 半導体メモリ回路
EP0678869B1 (de) * 1994-02-18 1999-07-07 STMicroelectronics S.r.l. Verfahren und Schaltung für Ladetaktsteuerung für nichflüchtige Speicherausgabedaten
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
JP3180883B2 (ja) * 1995-04-24 2001-06-25 日本電気株式会社 半導体記憶装置
KR0167247B1 (ko) * 1995-07-15 1999-02-01 문정환 디램의 지연 특성 보상 회로
KR100549934B1 (ko) * 1998-11-07 2006-05-16 삼성전자주식회사 반도체 메모리 장치의 워드라인 디코딩 회로
JP4100985B2 (ja) * 2002-07-16 2008-06-11 Ｎｅｃエレクトロニクス株式会社 データ処理装置、半導体記憶装置及びクロック周波数検出方法
JP5376704B2 (ja) * 2003-12-12 2013-12-25 株式会社半導体エネルギー研究所 半導体装置
FR2874734A1 (fr) * 2004-08-26 2006-03-03 St Microelectronics Sa Procede de lecture de cellules memoire programmables et effacables electriquement, a precharge anticipee de lignes de bit
US7260755B2 (en) * 2005-03-03 2007-08-21 International Business Machines Corporation Skewed inverter delay line for use in measuring critical paths in an integrated circuit
KR100712546B1 (ko) * 2006-01-12 2007-05-02 삼성전자주식회사 동기식 반도체 메모리 장치의 기입 데이터 마스크 신호발생 회로 및 기입 데이터 마스크 신호 발생 방법
US7286423B2 (en) * 2006-02-27 2007-10-23 Freescale Semiconductor, Inc. Bit line precharge in embedded memory
US7940545B2 (en) * 2008-06-24 2011-05-10 Freescale Semiconductor, Inc. Low power read scheme for read only memory (ROM)
US9196330B2 (en) 2012-01-17 2015-11-24 Qualcomm Incorporated Mimicking multi-voltage domain wordline decoding logic for a memory array
US8811109B2 (en) 2012-02-27 2014-08-19 Qualcomm Incorporated Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods
US10127979B2 (en) 2016-03-11 2018-11-13 Western Digital Technologies, Inc. Memory cell located pulse generator
US10381408B2 (en) 2016-03-24 2019-08-13 Western Digital Technologies, Inc. Method to fabricate discrete vertical transistors

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DE1160892B (de) * 1959-10-06 1964-01-09 Ibm Schiebeeinheit
US3996481A (en) * 1974-11-19 1976-12-07 International Business Machines Corporation FET load gate compensator
US4135160A (en) * 1977-05-27 1979-01-16 Tektronix, Inc. Pulse width normalizer
JPH0831278B2 (ja) * 1981-03-09 1996-03-27 富士通株式会社 メモリ回路
US4583008A (en) * 1983-02-25 1986-04-15 Harris Corporation Retriggerable edge detector for edge-actuated internally clocked parts
US4558435A (en) * 1983-05-31 1985-12-10 Rca Corporation Memory system
JPH0713878B2 (ja) * 1985-06-20 1995-02-15 三菱電機株式会社 Ｃｍｏｓトランジスタ回路
US4794570A (en) * 1986-07-02 1988-12-27 Digital Equipment Corporation Self-timed programmable logic array with pre-charge circuit
JPS6325894A (ja) * 1986-07-18 1988-02-03 Hitachi Ltd 半導体記憶装置
US4769791A (en) * 1986-08-06 1988-09-06 Advanced Micro Devices, Inc. On-chip pulse-width control circuit for SRAM memories
JPH01171194A (ja) * 1987-12-25 1989-07-06 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US4857868A (en) * 1988-03-30 1989-08-15 Rockwell International Corporation Data driven clock generator
US5208783A (en) * 1988-04-05 1993-05-04 Matsushita Electric Industrial Co., Ltd. Memory unit delay-compensating circuit
JPH01256093A (ja) * 1988-04-05 1989-10-12 Matsushita Electric Ind Co Ltd レジスタファイル
JP2525455B2 (ja) * 1988-05-30 1996-08-21 富士通株式会社 半導体メモリ装置
US5018111A (en) * 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
JP2575899B2 (ja) * 1989-10-26 1997-01-29 株式会社東芝 プリチャージ式論理回路
US4973865A (en) * 1989-12-20 1990-11-27 Vlsi Technology, Inc. Auto-delay gain circuit
US5172010A (en) * 1991-06-07 1992-12-15 International Business Machines Corp. Clock chopper/stretcher for high end machines

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10128757A1 (de) * 2001-06-13 2003-01-02 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Regeln der Betriebsspannung einer Digitalschaltung
DE10128757B4 (de) * 2001-06-13 2005-03-03 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum Regeln der Betriebsspannung einer Digitalschaltung
US7110932B2 (en) 2001-06-13 2006-09-19 Infineon Technologies Ag. Method and circuit arrangement for regulating the operating voltage of a digital circuit

Also Published As

Publication number Publication date
KR970000362B1 (ko) 1997-01-08
US5386150A (en) 1995-01-31
KR930010996A (ko) 1993-06-23
JPH05210983A (ja) 1993-08-20
EP0543269B1 (de) 1998-01-28
EP0543269A2 (de) 1993-05-26
EP0543269A3 (en) 1993-10-27
DE69224270D1 (de) 1998-03-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee