DE68921016D1 - Vorrichtung zum schnellen Auswählen eines lokalen Speichers. - Google Patents

Vorrichtung zum schnellen Auswählen eines lokalen Speichers.

Info

Publication number
DE68921016D1
DE68921016D1 DE68921016T DE68921016T DE68921016D1 DE 68921016 D1 DE68921016 D1 DE 68921016D1 DE 68921016 T DE68921016 T DE 68921016T DE 68921016 T DE68921016 T DE 68921016T DE 68921016 D1 DE68921016 D1 DE 68921016D1
Authority
DE
Germany
Prior art keywords
local memory
quickly selecting
quickly
selecting
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921016T
Other languages
English (en)
Other versions
DE68921016T2 (de
Inventor
Tiziano Maccianti
Angelo Oldani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA
Application granted granted Critical
Publication of DE68921016D1 publication Critical patent/DE68921016D1/de
Publication of DE68921016T2 publication Critical patent/DE68921016T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE68921016T 1988-03-15 1989-02-25 Vorrichtung zum schnellen Auswählen eines lokalen Speichers. Expired - Fee Related DE68921016T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8819770A IT1216085B (it) 1988-03-15 1988-03-15 Apparato di selezione veloce di memoria locale.

Publications (2)

Publication Number Publication Date
DE68921016D1 true DE68921016D1 (de) 1995-03-23
DE68921016T2 DE68921016T2 (de) 1995-06-01

Family

ID=11161083

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921016T Expired - Fee Related DE68921016T2 (de) 1988-03-15 1989-02-25 Vorrichtung zum schnellen Auswählen eines lokalen Speichers.

Country Status (4)

Country Link
US (1) US5115498A (de)
EP (1) EP0332911B1 (de)
DE (1) DE68921016T2 (de)
IT (1) IT1216085B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69133251T2 (de) * 1990-06-07 2004-01-15 Lg Electronics Inc Verfahren und gerät zur verwaltung von speicherzugriffen auf seite null in einem mehrprozessorsystem
US5410654A (en) * 1991-07-22 1995-04-25 International Business Machines Corporation Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals
DE69326236T2 (de) * 1993-06-16 1999-12-30 Bull Hn Information Syst Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4050094A (en) * 1976-04-30 1977-09-20 International Business Machines Corporation Translator lookahead controls
IT1183808B (it) * 1985-04-30 1987-10-22 Olivetti & Co Spa Circuito elettronico per collegare un microprocessore ad una memoria ad elevata capacita
US4868739A (en) * 1986-05-05 1989-09-19 International Business Machines Corporation Fixed clock rate vector processor having exclusive time cycle control programmable into each microword
IT1223142B (it) * 1987-11-17 1990-09-12 Honeywell Bull Spa Sistema multiprocessore di elaborazione con multiplazione di dati globali
US4961172A (en) * 1988-08-11 1990-10-02 Waferscale Integration, Inc. Decoder for a memory address bus

Also Published As

Publication number Publication date
EP0332911A3 (en) 1990-10-31
IT1216085B (it) 1990-02-22
EP0332911A2 (de) 1989-09-20
IT8819770A0 (it) 1988-03-15
DE68921016T2 (de) 1995-06-01
EP0332911B1 (de) 1995-02-08
US5115498A (en) 1992-05-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee