DE69224009D1 - Verfahren zur Herstellung einer Halbleiterstruktur mit MOS- und Bipolar-Bauteilen - Google Patents
Verfahren zur Herstellung einer Halbleiterstruktur mit MOS- und Bipolar-BauteilenInfo
- Publication number
- DE69224009D1 DE69224009D1 DE69224009T DE69224009T DE69224009D1 DE 69224009 D1 DE69224009 D1 DE 69224009D1 DE 69224009 T DE69224009 T DE 69224009T DE 69224009 T DE69224009 T DE 69224009T DE 69224009 D1 DE69224009 D1 DE 69224009D1
- Authority
- DE
- Germany
- Prior art keywords
- mos
- manufacturing
- semiconductor structure
- bipolar components
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/712,776 US5134082A (en) | 1991-06-10 | 1991-06-10 | Method of fabricating a semiconductor structure having MOS and bipolar devices |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69224009D1 true DE69224009D1 (de) | 1998-02-19 |
DE69224009T2 DE69224009T2 (de) | 1998-07-09 |
Family
ID=24863520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69224009T Expired - Fee Related DE69224009T2 (de) | 1991-06-10 | 1992-06-09 | Verfahren zur Herstellung einer Halbleiterstruktur mit MOS- und Bipolar-Bauteilen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5134082A (de) |
EP (1) | EP0518611B1 (de) |
JP (1) | JP3200169B2 (de) |
KR (1) | KR100243954B1 (de) |
DE (1) | DE69224009T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5227317A (en) * | 1989-04-21 | 1993-07-13 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit bipolar transistor device |
JPH0828424B2 (ja) * | 1990-11-06 | 1996-03-21 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH05308128A (ja) * | 1992-04-30 | 1993-11-19 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
US5294558A (en) * | 1993-06-01 | 1994-03-15 | International Business Machines Corporation | Method of making double-self-aligned bipolar transistor structure |
US5405790A (en) * | 1993-11-23 | 1995-04-11 | Motorola, Inc. | Method of forming a semiconductor structure having MOS, bipolar, and varactor devices |
US5618688A (en) * | 1994-02-22 | 1997-04-08 | Motorola, Inc. | Method of forming a monolithic semiconductor integrated circuit having an N-channel JFET |
JP3256084B2 (ja) * | 1994-05-26 | 2002-02-12 | 株式会社半導体エネルギー研究所 | 半導体集積回路およびその作製方法 |
US5465006A (en) * | 1994-07-15 | 1995-11-07 | Hewlett-Packard Company | Bipolar stripe transistor structure |
EP0871215A1 (de) * | 1997-04-08 | 1998-10-14 | Matsushita Electronics Corporation | Herstellungsverfahren für eine integrierte Halbleiterschaltvorrichtung |
US6271070B2 (en) * | 1997-12-25 | 2001-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
KR100285701B1 (ko) * | 1998-06-29 | 2001-04-02 | 윤종용 | 트렌치격리의제조방법및그구조 |
US6611044B2 (en) | 1998-09-11 | 2003-08-26 | Koninklijke Philips Electronics N.V. | Lateral bipolar transistor and method of making same |
KR20000023299A (ko) * | 1998-09-22 | 2000-04-25 | 다니엘 이. 박서 | 게이트 산화물 및 비정질 실리콘 전극을 원 위치에데포지트하는 방법 및 그에 해당하는 구조 |
WO2003017340A2 (en) * | 2001-08-15 | 2003-02-27 | Koninklijke Philips Electronics N.V. | A method for concurrent fabrication of a double polysilicon bipolar transistor and a base polysilicon resistor |
US7612387B2 (en) * | 2005-12-16 | 2009-11-03 | Stmicroelectronics S.A. | Thyristor optimized for a sinusoidal HF control |
KR100793607B1 (ko) * | 2006-06-27 | 2008-01-10 | 매그나칩 반도체 유한회사 | 에피텍셜 실리콘 웨이퍼 및 그 제조방법 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4707456A (en) * | 1985-09-18 | 1987-11-17 | Advanced Micro Devices, Inc. | Method of making a planar structure containing MOS and bipolar transistors |
US4808548A (en) * | 1985-09-18 | 1989-02-28 | Advanced Micro Devices, Inc. | Method of making bipolar and MOS devices on same integrated circuit substrate |
EP0256315B1 (de) * | 1986-08-13 | 1992-01-29 | Siemens Aktiengesellschaft | Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung |
JPS6350070A (ja) * | 1986-08-19 | 1988-03-02 | Matsushita Electronics Corp | 縦型mos電界効果トランジスタ |
US4837176A (en) * | 1987-01-30 | 1989-06-06 | Motorola Inc. | Integrated circuit structures having polycrystalline electrode contacts and process |
JPS63239856A (ja) * | 1987-03-27 | 1988-10-05 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
US4803175A (en) * | 1987-09-14 | 1989-02-07 | Motorola Inc. | Method of fabricating a bipolar semiconductor device with silicide contacts |
US4830973A (en) * | 1987-10-06 | 1989-05-16 | Motorola, Inc. | Merged complementary bipolar and MOS means and method |
JPH01202855A (ja) * | 1988-02-09 | 1989-08-15 | Matsushita Electron Corp | 半導体集積回路の製造方法 |
US5008210A (en) * | 1989-02-07 | 1991-04-16 | Hewlett-Packard Company | Process of making a bipolar transistor with a trench-isolated emitter |
JPH02246264A (ja) * | 1989-03-20 | 1990-10-02 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH0330334A (ja) * | 1989-06-28 | 1991-02-08 | Toshiba Corp | バイポーラトランジスタの製造方法 |
US4902639A (en) * | 1989-08-03 | 1990-02-20 | Motorola, Inc. | Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts |
US5079177A (en) * | 1989-09-19 | 1992-01-07 | National Semiconductor Corporation | Process for fabricating high performance bicmos circuits |
US4960726A (en) * | 1989-10-19 | 1990-10-02 | International Business Machines Corporation | BiCMOS process |
US5037768A (en) * | 1990-02-12 | 1991-08-06 | Motorola, Inc. | Method of fabricating a double polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors |
US4987089A (en) * | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
-
1991
- 1991-06-10 US US07/712,776 patent/US5134082A/en not_active Expired - Fee Related
-
1992
- 1992-03-30 KR KR1019920005233A patent/KR100243954B1/ko not_active IP Right Cessation
- 1992-06-05 JP JP16997292A patent/JP3200169B2/ja not_active Expired - Fee Related
- 1992-06-09 EP EP92305271A patent/EP0518611B1/de not_active Expired - Lifetime
- 1992-06-09 DE DE69224009T patent/DE69224009T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0518611A3 (en) | 1993-11-18 |
JP3200169B2 (ja) | 2001-08-20 |
JPH05198752A (ja) | 1993-08-06 |
DE69224009T2 (de) | 1998-07-09 |
KR930020663A (ko) | 1993-10-20 |
EP0518611A2 (de) | 1992-12-16 |
EP0518611B1 (de) | 1998-01-14 |
KR100243954B1 (ko) | 2000-02-01 |
US5134082A (en) | 1992-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69232432D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE69231803D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE69015216D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE69403593D1 (de) | Gerät und Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE69128554D1 (de) | Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit niedrig dotiertem Drain und eine MOS-integrierte Schaltungsstruktur | |
DE68929150D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE68924366D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE69032773D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE69317800D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE69421592D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE69216752D1 (de) | Verfahren zur Herstellung einer Halbleiter-Scheibe | |
DE69330980D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE69023558D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE69224009D1 (de) | Verfahren zur Herstellung einer Halbleiterstruktur mit MOS- und Bipolar-Bauteilen | |
DE69229661D1 (de) | Verfahren zur Herstellung einer Anschlusstruktur für eine Halbleiteranordnung | |
DE69323979D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE69528107D1 (de) | Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einem Feldeffekttransistor, einem Kondensator und einem Widerstand. | |
DE69016955D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung. | |
DE69508885D1 (de) | Halbleiterdiode und Verfahren zur Herstellung | |
DE69030709D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE68928951D1 (de) | Verfahren zur Herstellung einer integrierten Schaltung mit Bipolartransistoren | |
DE69229314D1 (de) | Halbleiteranordnung und Verfahren zur Herstellung | |
DE69231653D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung mit Isolierzonen | |
DE69031702D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung | |
DE68911453D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung mit Wellenleiterstruktur. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN |
|
8339 | Ceased/non-payment of the annual fee |