DE69128554D1 - Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit niedrig dotiertem Drain und eine MOS-integrierte Schaltungsstruktur - Google Patents

Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit niedrig dotiertem Drain und eine MOS-integrierte Schaltungsstruktur

Info

Publication number
DE69128554D1
DE69128554D1 DE69128554T DE69128554T DE69128554D1 DE 69128554 D1 DE69128554 D1 DE 69128554D1 DE 69128554 T DE69128554 T DE 69128554T DE 69128554 T DE69128554 T DE 69128554T DE 69128554 D1 DE69128554 D1 DE 69128554D1
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit structure
producing
doped drain
low doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128554T
Other languages
English (en)
Other versions
DE69128554T2 (de
Inventor
Israel Beinglass
John Borland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of DE69128554D1 publication Critical patent/DE69128554D1/de
Application granted granted Critical
Publication of DE69128554T2 publication Critical patent/DE69128554T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69128554T 1990-04-06 1991-03-22 Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit niedrig dotiertem Drain und eine MOS-integrierte Schaltungsstruktur Expired - Fee Related DE69128554T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/505,745 US4975385A (en) 1990-04-06 1990-04-06 Method of constructing lightly doped drain (LDD) integrated circuit structure

Publications (2)

Publication Number Publication Date
DE69128554D1 true DE69128554D1 (de) 1998-02-12
DE69128554T2 DE69128554T2 (de) 1998-08-13

Family

ID=24011650

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128554T Expired - Fee Related DE69128554T2 (de) 1990-04-06 1991-03-22 Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit niedrig dotiertem Drain und eine MOS-integrierte Schaltungsstruktur

Country Status (5)

Country Link
US (1) US4975385A (de)
EP (1) EP0450432B1 (de)
JP (1) JP2862696B2 (de)
KR (1) KR100212871B1 (de)
DE (1) DE69128554T2 (de)

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US5238858A (en) * 1988-10-31 1993-08-24 Sharp Kabushiki Kaisha Ion implantation method
US5082794A (en) * 1989-02-13 1992-01-21 Motorola, Inc. Method of fabricating mos transistors using selective polysilicon deposition
EP0459770B1 (de) * 1990-05-31 1995-05-03 Canon Kabushiki Kaisha Verfahren zur Herstellung einer Halbleiteranordnung mit Gatestruktur
KR940001402B1 (ko) * 1991-04-10 1994-02-21 삼성전자 주식회사 골드구조를 가지는 반도체소자의 제조방법
US5324680A (en) * 1991-05-22 1994-06-28 Samsung Electronics, Co. Ltd. Semiconductor memory device and the fabrication method thereof
US5194926A (en) * 1991-10-03 1993-03-16 Motorola Inc. Semiconductor device having an inverse-T bipolar transistor
US5580808A (en) * 1992-07-30 1996-12-03 Canon Kabushiki Kaisha Method of manufacturing a ROM device having contact holes treated with hydrogen atoms and energy beam
US5411907A (en) * 1992-09-01 1995-05-02 Taiwan Semiconductor Manufacturing Company Capping free metal silicide integrated process
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
US5308780A (en) * 1993-07-22 1994-05-03 United Microelectronics Corporation Surface counter-doped N-LDD for high hot carrier reliability
KR0124626B1 (ko) * 1994-02-01 1997-12-11 문정환 박막 트랜지스터 제조방법
US5409848A (en) * 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US5424226A (en) * 1994-04-11 1995-06-13 Xerox Corporation Method of fabricating NMOS and PMOS FET's in a CMOS process
JP2692617B2 (ja) * 1994-12-06 1997-12-17 日本電気株式会社 半導体装置の製造方法
US5817564A (en) * 1996-06-28 1998-10-06 Harris Corporation Double diffused MOS device and method
US5714786A (en) 1996-10-31 1998-02-03 Micron Technology, Inc. Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors
US5866448A (en) * 1997-07-30 1999-02-02 Chartered Semiconductor Manufacturing Ltd. Procedure for forming a lightly-doped-drain structure using polymer layer
US6121120A (en) * 1997-08-07 2000-09-19 Nec Corporation Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer
US6117742A (en) * 1998-05-15 2000-09-12 Advanced Micro Devices, Inc. Method for making a high performance transistor
KR100351441B1 (ko) * 1998-06-08 2002-12-18 주식회사 하이닉스반도체 반도체소자의트랜지스터형성방법
JPH11354541A (ja) * 1998-06-11 1999-12-24 Fujitsu Quantum Devices Kk 半導体装置およびその製造方法
US5981346A (en) * 1999-03-17 1999-11-09 National Semiconductor Corporation Process for forming physical gate length dependent implanted regions using dual polysilicon spacers
US6309937B1 (en) * 1999-05-03 2001-10-30 Vlsi Technology, Inc. Method of making shallow junction semiconductor devices
JP4666723B2 (ja) 1999-07-06 2011-04-06 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6864143B1 (en) * 2000-01-24 2005-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate bridging between gate and source/drain in cobalt salicidation
US7274076B2 (en) * 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
KR100596880B1 (ko) * 2004-09-01 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 게이트 형성 방법
GB2451116A (en) * 2007-07-20 2009-01-21 X Fab Uk Ltd Polysilicon devices
US8072049B2 (en) 2009-04-24 2011-12-06 Fairchild Semiconductor Corporation Polysilicon drift fuse
CN102403256B (zh) * 2010-09-08 2014-02-26 上海华虹宏力半导体制造有限公司 赝埋层及制造方法、深孔接触及三极管
US11152381B1 (en) * 2020-04-13 2021-10-19 HeFeChip Corporation Limited MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same
US11114140B1 (en) 2020-04-23 2021-09-07 HeFeChip Corporation Limited One time programmable (OTP) bits for physically unclonable functions
US11437082B2 (en) 2020-05-17 2022-09-06 HeFeChip Corporation Limited Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage
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Also Published As

Publication number Publication date
EP0450432B1 (de) 1998-01-07
JPH04225529A (ja) 1992-08-14
EP0450432A1 (de) 1991-10-09
KR100212871B1 (ko) 1999-08-02
JP2862696B2 (ja) 1999-03-03
DE69128554T2 (de) 1998-08-13
KR910019114A (ko) 1991-11-30
US4975385A (en) 1990-12-04

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