DE69214339D1 - Struktur und Verfahren für die Bildung selbstjustierender Kontakte - Google Patents

Struktur und Verfahren für die Bildung selbstjustierender Kontakte

Info

Publication number
DE69214339D1
DE69214339D1 DE69214339T DE69214339T DE69214339D1 DE 69214339 D1 DE69214339 D1 DE 69214339D1 DE 69214339 T DE69214339 T DE 69214339T DE 69214339 T DE69214339 T DE 69214339T DE 69214339 D1 DE69214339 D1 DE 69214339D1
Authority
DE
Germany
Prior art keywords
procedure
establishing self
aligning contacts
aligning
contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69214339T
Other languages
English (en)
Other versions
DE69214339T2 (de
Inventor
Che Chia Wei
Chiara Zaccherini
Robert Otis Miller
Girish Anant Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69214339D1 publication Critical patent/DE69214339D1/de
Application granted granted Critical
Publication of DE69214339T2 publication Critical patent/DE69214339T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69214339T 1991-03-05 1992-02-28 Struktur und Verfahren für die Bildung selbstjustierender Kontakte Expired - Fee Related DE69214339T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66525391A 1991-03-05 1991-03-05

Publications (2)

Publication Number Publication Date
DE69214339D1 true DE69214339D1 (de) 1996-11-14
DE69214339T2 DE69214339T2 (de) 1997-02-27

Family

ID=24669350

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69214339T Expired - Fee Related DE69214339T2 (de) 1991-03-05 1992-02-28 Struktur und Verfahren für die Bildung selbstjustierender Kontakte

Country Status (5)

Country Link
US (1) US5278098A (de)
EP (1) EP0507446B1 (de)
JP (1) JPH0582661A (de)
KR (1) KR100228619B1 (de)
DE (1) DE69214339T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03141645A (ja) * 1989-07-10 1991-06-17 Texas Instr Inc <Ti> ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子
US5536683A (en) * 1995-06-15 1996-07-16 United Microelectronics Corporation Method for interconnecting semiconductor devices
US5554549A (en) * 1995-07-03 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Salicide process for FETs
US5834811A (en) * 1996-06-17 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide process for FETs
GB2320134A (en) * 1996-12-04 1998-06-10 United Microelectronics Corp Salicide electrodes for semiconductor devices
US6048763A (en) 1997-08-21 2000-04-11 Micron Technology, Inc. Integrated capacitor bottom electrode with etch stop layer
US6010935A (en) * 1997-08-21 2000-01-04 Micron Technology, Inc. Self aligned contacts
US6147405A (en) 1998-02-19 2000-11-14 Micron Technology, Inc. Asymmetric, double-sided self-aligned silicide and method of forming the same
US6100185A (en) * 1998-08-14 2000-08-08 Micron Technology, Inc. Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
US6524951B2 (en) * 1999-03-01 2003-02-25 Micron Technology, Inc. Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
US6365507B1 (en) 1999-03-01 2002-04-02 Micron Technology, Inc. Method of forming integrated circuitry
US7153772B2 (en) * 2003-06-12 2006-12-26 Asm International N.V. Methods of forming silicide films in semiconductor devices
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US8367548B2 (en) 2007-03-16 2013-02-05 Asm America, Inc. Stable silicide films and methods for making the same
US7927942B2 (en) 2008-12-19 2011-04-19 Asm International N.V. Selective silicide process
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US8367528B2 (en) * 2009-11-17 2013-02-05 Asm America, Inc. Cyclical epitaxial deposition and etch
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE216577C (de) *
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
JPS551157A (en) * 1978-09-11 1980-01-07 Hitachi Ltd Method of fabricating semiconductor device
JPS57112027A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
JPH0666427B2 (ja) * 1983-09-16 1994-08-24 セイコーエプソン株式会社 Ｍｏｓ型半導体集積回路装置の製造方法
JPS59130442A (ja) * 1983-11-28 1984-07-27 Hitachi Ltd 半導体装置の製造方法
JPS62260340A (ja) * 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
JPS6316672A (ja) * 1986-07-09 1988-01-23 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPS63211742A (ja) * 1987-02-27 1988-09-02 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6465873A (en) * 1987-09-07 1989-03-13 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JPH01302748A (ja) * 1988-05-30 1989-12-06 Sharp Corp 半導体装置の製造方法
JPH0290611A (ja) * 1988-09-28 1990-03-30 Matsushita Electron Corp 半導体装置の製造方法
JPH02110933A (ja) * 1988-10-19 1990-04-24 Matsushita Electron Corp 配線構造とその形成方法
KR930004295B1 (ko) * 1988-12-24 1993-05-22 삼성전자 주식회사 Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법
US4966864A (en) * 1989-03-27 1990-10-30 Motorola, Inc. Contact structure and method

Also Published As

Publication number Publication date
KR920018843A (ko) 1992-10-22
JPH0582661A (ja) 1993-04-02
DE69214339T2 (de) 1997-02-27
EP0507446A2 (de) 1992-10-07
KR100228619B1 (ko) 1999-11-01
US5278098A (en) 1994-01-11
EP0507446B1 (de) 1996-10-09
EP0507446A3 (en) 1993-02-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee