DE69031362D1 - Verzögerungsfehler-Testvorrichtung - Google Patents

Verzögerungsfehler-Testvorrichtung

Info

Publication number
DE69031362D1
DE69031362D1 DE69031362T DE69031362T DE69031362D1 DE 69031362 D1 DE69031362 D1 DE 69031362D1 DE 69031362 T DE69031362 T DE 69031362T DE 69031362 T DE69031362 T DE 69031362T DE 69031362 D1 DE69031362 D1 DE 69031362D1
Authority
DE
Germany
Prior art keywords
input
flop
flip
latch
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031362T
Other languages
English (en)
Other versions
DE69031362T2 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69031362D1 publication Critical patent/DE69031362D1/de
Publication of DE69031362T2 publication Critical patent/DE69031362T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69031362T 1989-06-09 1990-06-07 Verzögerungsfehler-Testvorrichtung Expired - Fee Related DE69031362T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/364,915 US5056094A (en) 1989-06-09 1989-06-09 Delay fault testing method and apparatus

Publications (2)

Publication Number Publication Date
DE69031362D1 true DE69031362D1 (de) 1997-10-09
DE69031362T2 DE69031362T2 (de) 1998-01-08

Family

ID=23436657

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031362T Expired - Fee Related DE69031362T2 (de) 1989-06-09 1990-06-07 Verzögerungsfehler-Testvorrichtung

Country Status (4)

Country Link
US (1) US5056094A (de)
EP (1) EP0402134B1 (de)
JP (1) JP3340736B2 (de)
DE (1) DE69031362T2 (de)

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US5422891A (en) * 1993-07-23 1995-06-06 Rutgers University Robust delay fault built-in self-testing method and apparatus
US5583787A (en) * 1994-03-08 1996-12-10 Motorola Inc. Method and data processing system for determining electrical circuit path delays
US5544175A (en) * 1994-03-15 1996-08-06 Hewlett-Packard Company Method and apparatus for the capturing and characterization of high-speed digital information
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US6055659A (en) * 1999-02-26 2000-04-25 Texas Instruments Incorporated Boundary scan with latching output buffer and weak input buffer
US5596585A (en) * 1995-06-07 1997-01-21 Advanced Micro Devices, Inc. Performance driven BIST technique
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DE69606129T3 (de) * 1995-10-13 2015-03-05 Jtag Technologies B.V. Verfahren und Tester zur Beaufschlagung eines elektronischen Bausteins mit einem Triggerimpuls
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
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US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US5886901A (en) * 1997-01-07 1999-03-23 Lsi Logic Corporation Flip-flop for scan test chain
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US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
US6081913A (en) * 1997-06-03 2000-06-27 Sun Microsystems, Inc. Method for ensuring mutual exclusivity of selected signals during application of test patterns
US6314470B1 (en) * 1997-07-25 2001-11-06 Hewlett Packard Company System and method for asynchronously accessing a graphics system for graphics application evaluation and control
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6185710B1 (en) 1998-03-30 2001-02-06 International Business Machines Corporation High-performance IEEE1149.1-compliant boundary scan cell
GB9810512D0 (en) * 1998-05-15 1998-07-15 Sgs Thomson Microelectronics Detecting communication errors across a chip boundary
US6560734B1 (en) 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
US6519729B1 (en) 1998-06-27 2003-02-11 Texas Instruments Incorporated Reduced power testing with equally divided scan paths
JP2000258506A (ja) * 1999-03-12 2000-09-22 Mitsubishi Electric Corp 半導体集積回路およびそのテストパターン生成方法
DE19938060B4 (de) * 1999-08-12 2008-06-19 Nokia Siemens Networks Gmbh & Co.Kg Integrierte Schaltung mit einer Testeinrichtung und Verfahren zum Testen der Güte elektrischer Verbindungen der ingegrierten Schaltung
JP4789297B2 (ja) * 1999-11-29 2011-10-12 パナソニック株式会社 半導体集積回路のテストパターン生成方法
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6567943B1 (en) * 2000-04-07 2003-05-20 International Business Machines Corporation D flip-flop structure with flush path for high-speed boundary scan applications
DE10033349A1 (de) * 2000-07-08 2002-01-17 Bosch Gmbh Robert Verfahren und Anordnung zum Testen digitaler Schaltungen
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6701476B2 (en) * 2001-05-29 2004-03-02 Motorola, Inc. Test access mechanism for supporting a configurable built-in self-test circuit and method thereof
US20020194565A1 (en) * 2001-06-18 2002-12-19 Karim Arabi Simultaneous built-in self-testing of multiple identical blocks of integrated circuitry
EP1296152A1 (de) * 2001-09-21 2003-03-26 Siemens Aktiengesellschaft Elektronischer Baustein und Verfahren zu dessen Qualifizierungsmessung
DE10201431C1 (de) * 2002-01-16 2003-08-21 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Betrieb einer Testanordnung mit einer integrierten Schaltung
JP2003233639A (ja) * 2002-02-06 2003-08-22 Mitsubishi Electric Corp 故障検証装置、故障検証方法および故障解析手法
US7028238B2 (en) 2002-04-18 2006-04-11 Lsi Logic Corporation Input/output characterization chain for an integrated circuit
US7398445B2 (en) * 2002-08-09 2008-07-08 Synplicity, Inc. Method and system for debug and test using replicated logic
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
US6904576B2 (en) * 2002-08-09 2005-06-07 Synplicity, Inc. Method and system for debugging using replicated logic
US20040199838A1 (en) * 2003-03-19 2004-10-07 Rutkowski Paul William Enhanced boundary-scan method and apparatus providing tester channel reduction
DE10335809B4 (de) * 2003-08-05 2010-07-01 Infineon Technologies Ag Integrierte Schaltung mit einem zu testenden elektronischen Schaltkreis und Testsystem-Anordnung zum Testen der integrierten Schaltung
US7162673B2 (en) 2003-11-14 2007-01-09 Integrated Device Technology, Inc. Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
EP1810044B1 (de) * 2004-07-28 2009-04-29 Nxp B.V. Schaltungsverbindungs-prüfanordnung und ansatz dafür
US7475309B2 (en) * 2005-06-30 2009-01-06 Intel Corporation Parallel test mode for multi-core processors
JP2007011957A (ja) * 2005-07-04 2007-01-18 Nec Electronics Corp 回路設計装置およびプログラム
US7348797B2 (en) * 2005-08-30 2008-03-25 Texas Instruments Incorporated Functional cells for automated I/O timing characterization of an integrated circuit
JP4299856B2 (ja) * 2006-12-14 2009-07-22 エルピーダメモリ株式会社 半導体装置
JP2012026950A (ja) * 2010-07-27 2012-02-09 Sony Corp 集積半導体装置
US9454468B2 (en) * 2014-06-27 2016-09-27 Wipro Limited Method and system for testing software
KR102546302B1 (ko) * 2016-07-08 2023-06-21 삼성전자주식회사 클락 지터 측정 회로 및 이를 포함하는 반도체 장치
US11749368B2 (en) * 2019-12-27 2023-09-05 Intel Corporation Quick configurable universal register for a configurable integrated circuit die

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JPH0760400B2 (ja) * 1986-01-07 1995-06-28 株式会社日立製作所 論理回路の診断方法
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Also Published As

Publication number Publication date
JP3340736B2 (ja) 2002-11-05
DE69031362T2 (de) 1998-01-08
EP0402134A3 (de) 1991-09-04
EP0402134B1 (de) 1997-09-03
EP0402134A2 (de) 1990-12-12
US5056094A (en) 1991-10-08
JPH03103781A (ja) 1991-04-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee