JP4299856B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4299856B2 JP4299856B2 JP2006336590A JP2006336590A JP4299856B2 JP 4299856 B2 JP4299856 B2 JP 4299856B2 JP 2006336590 A JP2006336590 A JP 2006336590A JP 2006336590 A JP2006336590 A JP 2006336590A JP 4299856 B2 JP4299856 B2 JP 4299856B2
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 238000012360 testing method Methods 0.000 claims description 76
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 34
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- 238000012545 processing Methods 0.000 description 2
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- -1 tungsten nitride Chemical class 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
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- Semiconductor Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
半導体装置に関する。
101:テストモードデコード&ラッチ回路
102:モード信号使用回路
103:テストモード信号配線(TEST1信号配線)
104:通常信号配線(/SIG1信号配線)
105:ラッチ回路
106、107、108:バッファ(インバータ)
109:/TMRS信号配線
151:スイッチング用バッファ
152:フリップフロップ
153、154:インバータ(バッファ)
Claims (7)
- タイミング信号に基づくタイミングで所定の信号を発生する信号発生回路と、
前記信号発生回路が出力する所定の信号に基づいて、該入力した所定の信号に応じた動作を行う信号使用回路と、
前記信号発生回路と前記信号使用回路との間を接続し、前記信号発生回路に接続された高抵抗配線部分と、該高抵抗配線部分と前記信号使用回路との間に接続された、前記高抵抗配線部分よりもインピーダンスが低い低抵抗配線部分とを含む信号配線と、
前記信号配線の低抵抗配線部分に挿入され、前記タイミング信号に基づいて、前記信号発生回路が出力する所定の信号をラッチするラッチ回路とを備えることを特徴とする半導体装置。 - 前記信号発生回路が、前記タイミング信号に基づくタイミングで入力外部信号をデコードし、モード信号を発生するモード信号発生回路である、請求項1に記載の半導体装置。
- 前記信号発生回路は、半導体装置における所定の動作時に使用され、半導体装置の通常動作状態では前記所定の信号を発生しない、請求項1又は2に記載の半導体装置。
- 前記信号発生回路は、半導体装置の内部テスト時に使用される、請求項3に記載の半導体装置。
- 前記ラッチ回路は、前記タイミング信号の発生時にのみ、前記信号発生回路から入力する所定の信号に応じた信号を出力するスイッチング用バッファと、該スイッチング用バッファが出力する信号を保持すると共に、該スイッチング用バッファの出力信号に応じた信号を出力するフリップフロップとを有する、請求項1〜4の何れか一に記載の半導体装置。
- 前記スイッチング用バッファは、前記タイミング信号の発生時は、前記信号発生回路から入力する所定の信号を反転して出力し、前記タイミング信号が発生しない期間では、入力信号に基づく信号出力を停止する、請求項5に記載の半導体装置。
- 前記フリップフロップが、前記スイッチング用バッファが出力する信号を反転して出力する第1のインバータと、該第1のインバータの出力を反転して前記第1のインバータの入力に戻す第2のインバータとを含む、請求項6に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006336590A JP4299856B2 (ja) | 2006-12-14 | 2006-12-14 | 半導体装置 |
US11/955,790 US7741862B2 (en) | 2006-12-14 | 2007-12-13 | Semiconductor device including a signal generator activated upon occurring of a timing signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006336590A JP4299856B2 (ja) | 2006-12-14 | 2006-12-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008153253A JP2008153253A (ja) | 2008-07-03 |
JP4299856B2 true JP4299856B2 (ja) | 2009-07-22 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006336590A Active JP4299856B2 (ja) | 2006-12-14 | 2006-12-14 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US7741862B2 (ja) |
JP (1) | JP4299856B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010187047A (ja) * | 2009-02-10 | 2010-08-26 | Renesas Electronics Corp | テスト回路、及びテスト方法 |
KR20120078998A (ko) * | 2011-01-03 | 2012-07-11 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 |
JP6572290B2 (ja) * | 2017-11-22 | 2019-09-04 | ファナック株式会社 | 電子機器の異常検出装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5056094A (en) * | 1989-06-09 | 1991-10-08 | Texas Instruments Incorporated | Delay fault testing method and apparatus |
KR930009490B1 (ko) * | 1991-07-15 | 1993-10-04 | 금성일렉트론 주식회사 | 순간 테스트 모드 지정회로 |
JP2919207B2 (ja) | 1992-12-07 | 1999-07-12 | 日本電気アイシーマイコンシステム株式会社 | 半導体装置の配線構造 |
JPH11163065A (ja) | 1997-12-01 | 1999-06-18 | Seiko Epson Corp | 半導体装置 |
JPH11353900A (ja) * | 1998-06-11 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置 |
JP4712183B2 (ja) * | 2000-11-30 | 2011-06-29 | 富士通セミコンダクター株式会社 | 同期型半導体装置、及び試験システム |
KR100732241B1 (ko) * | 2006-01-24 | 2007-06-27 | 삼성전자주식회사 | 테스트 효율이 높은 반도체 메모리 장치, 반도체 메모리장치의 테스트 방법, 및 이를 구비한 테스트 시스템 |
-
2006
- 2006-12-14 JP JP2006336590A patent/JP4299856B2/ja active Active
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2007
- 2007-12-13 US US11/955,790 patent/US7741862B2/en active Active
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Publication number | Publication date |
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JP2008153253A (ja) | 2008-07-03 |
US20080143371A1 (en) | 2008-06-19 |
US7741862B2 (en) | 2010-06-22 |
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