DE68927172T2 - Multiprozessorsystem mit cache-speichern - Google Patents

Multiprozessorsystem mit cache-speichern

Info

Publication number
DE68927172T2
DE68927172T2 DE68927172T DE68927172T DE68927172T2 DE 68927172 T2 DE68927172 T2 DE 68927172T2 DE 68927172 T DE68927172 T DE 68927172T DE 68927172 T DE68927172 T DE 68927172T DE 68927172 T2 DE68927172 T2 DE 68927172T2
Authority
DE
Germany
Prior art keywords
multiprocessor system
cache storage
cache
storage
multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68927172T
Other languages
English (en)
Other versions
DE68927172D1 (de
Inventor
Martin J Schwartz
Robert D Becker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22795556&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68927172(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Application granted granted Critical
Publication of DE68927172D1 publication Critical patent/DE68927172D1/de
Publication of DE68927172T2 publication Critical patent/DE68927172T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE68927172T 1988-06-30 1989-06-22 Multiprozessorsystem mit cache-speichern Expired - Lifetime DE68927172T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/213,556 US4939641A (en) 1988-06-30 1988-06-30 Multi-processor system with cache memories
PCT/US1989/002740 WO1990000285A1 (en) 1988-06-30 1989-06-22 Multi-processor system with cache memories

Publications (2)

Publication Number Publication Date
DE68927172D1 DE68927172D1 (de) 1996-10-17
DE68927172T2 true DE68927172T2 (de) 1997-04-24

Family

ID=22795556

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927172T Expired - Lifetime DE68927172T2 (de) 1988-06-30 1989-06-22 Multiprozessorsystem mit cache-speichern

Country Status (7)

Country Link
US (1) US4939641A (de)
EP (1) EP0422113B1 (de)
JP (2) JP3510240B2 (de)
AU (1) AU622471B2 (de)
CA (1) CA1320284C (de)
DE (1) DE68927172T2 (de)
WO (1) WO1990000285A1 (de)

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US6000017A (en) * 1995-01-20 1999-12-07 Intel Corporation Hybrid tag architecture for a cache memory
US5594863A (en) * 1995-06-26 1997-01-14 Novell, Inc. Method and apparatus for network file recovery
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US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US6021466A (en) * 1996-03-14 2000-02-01 Compaq Computer Corporation Transferring data between caches in a multiple processor environment
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US5937431A (en) * 1996-07-12 1999-08-10 Samsung Electronics Co., Ltd. Multi- node, multi-level cache- only memory architecture with relaxed inclusion
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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US5900016A (en) * 1997-04-02 1999-05-04 Opti Inc. System for using a cache memory with a write-back architecture
JPH1173370A (ja) * 1997-08-29 1999-03-16 Fujitsu Ltd 情報処理装置
US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
JP4179677B2 (ja) 1998-09-04 2008-11-12 株式会社ルネサステクノロジ マルチプロセッサ装置
JP2003505753A (ja) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) * 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
DE50310198D1 (de) 2002-02-18 2008-09-04 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US20110161977A1 (en) * 2002-03-21 2011-06-30 Martin Vorbach Method and device for data processing
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US20070150658A1 (en) * 2005-12-28 2007-06-28 Jaideep Moses Pinning locks in shared cache
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US8180968B2 (en) * 2007-03-28 2012-05-15 Oracle America, Inc. Reduction of cache flush time using a dirty line limiter
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Also Published As

Publication number Publication date
JP3510240B2 (ja) 2004-03-22
EP0422113A4 (en) 1992-03-25
AU3963689A (en) 1990-01-23
DE68927172D1 (de) 1996-10-17
WO1990000285A1 (en) 1990-01-11
AU622471B2 (en) 1992-04-09
CA1320284C (en) 1993-07-13
JPH04501027A (ja) 1992-02-20
EP0422113B1 (de) 1996-09-11
JP2002163148A (ja) 2002-06-07
EP0422113A1 (de) 1991-04-17
US4939641A (en) 1990-07-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: LG SEMICON CO., LTD., CHEONGJU, KR

8327 Change in the person/name/address of the patent owner

Owner name: LG ELECTRONICS INC., SEOUL/SOUL, KR

8328 Change in the person/name/address of the agent

Representative=s name: COHAUSZ & FLORACK, 40472 DUESSELDORF