DE68901356D1 - Cachespeicher mit pseudo-virtueller adressierung. - Google Patents

Cachespeicher mit pseudo-virtueller adressierung.

Info

Publication number
DE68901356D1
DE68901356D1 DE8989103355T DE68901356T DE68901356D1 DE 68901356 D1 DE68901356 D1 DE 68901356D1 DE 8989103355 T DE8989103355 T DE 8989103355T DE 68901356 T DE68901356 T DE 68901356T DE 68901356 D1 DE68901356 D1 DE 68901356D1
Authority
DE
Germany
Prior art keywords
cache storage
virtual addressing
pseudo virtual
pseudo
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8989103355T
Other languages
English (en)
Inventor
Ferruccio Zulian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA
Application granted granted Critical
Publication of DE68901356D1 publication Critical patent/DE68901356D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8989103355T 1988-03-15 1989-02-25 Cachespeicher mit pseudo-virtueller adressierung. Expired - Lifetime DE68901356D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8819771A IT1216086B (it) 1988-03-15 1988-03-15 Memoria tampone ad indirizzamento pseudo virtuale.

Publications (1)

Publication Number Publication Date
DE68901356D1 true DE68901356D1 (de) 1992-06-04

Family

ID=11161089

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8989103355T Expired - Lifetime DE68901356D1 (de) 1988-03-15 1989-02-25 Cachespeicher mit pseudo-virtueller adressierung.

Country Status (4)

Country Link
US (1) US5165028A (de)
EP (1) EP0332908B1 (de)
DE (1) DE68901356D1 (de)
IT (1) IT1216086B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748190B2 (ja) * 1990-01-22 1995-05-24 株式会社東芝 キャッシュメモリ内蔵マイクロプロセッサ
US5305444A (en) * 1990-12-21 1994-04-19 Sun Microsystems, Inc. Apparatus for increasing the number of hits in a translation lookaside buffer including instruction address lookaside register
US5479630A (en) * 1991-04-03 1995-12-26 Silicon Graphics Inc. Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same
GB2273179A (en) * 1992-12-02 1994-06-08 Ibm Cache indexing in interative processes.
US5784706A (en) * 1993-12-13 1998-07-21 Cray Research, Inc. Virtual to logical to physical address translation for distributed memory massively parallel processing systems
US5890221A (en) * 1994-10-05 1999-03-30 International Business Machines Corporation Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit
US6813699B1 (en) 1995-06-02 2004-11-02 Transmeta Corporation Speculative address translation for processor using segmentation and optional paging
US5895503A (en) 1995-06-02 1999-04-20 Belgard; Richard A. Address translation method and mechanism using physical address information including during a segmentation process
EP1046998A1 (de) * 1999-04-22 2000-10-25 Texas Instruments Incorporated Digitale Signalprozessoren mit virtueller Addressierung
GB2550903B (en) * 2016-05-27 2019-06-12 Arm Ip Ltd Context data control

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4737909A (en) * 1985-04-01 1988-04-12 National Semiconductor Corp. Cache memory address apparatus
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system

Also Published As

Publication number Publication date
IT8819771A0 (it) 1988-03-15
EP0332908B1 (de) 1992-04-29
EP0332908A1 (de) 1989-09-20
IT1216086B (it) 1990-02-22
US5165028A (en) 1992-11-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee