DE69021192D1 - Peripheres Massenspeichersubsystem. - Google Patents

Peripheres Massenspeichersubsystem.

Info

Publication number
DE69021192D1
DE69021192D1 DE69021192T DE69021192T DE69021192D1 DE 69021192 D1 DE69021192 D1 DE 69021192D1 DE 69021192 T DE69021192 T DE 69021192T DE 69021192 T DE69021192 T DE 69021192T DE 69021192 D1 DE69021192 D1 DE 69021192D1
Authority
DE
Germany
Prior art keywords
mass storage
storage subsystem
peripheral mass
peripheral
subsystem
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021192T
Other languages
English (en)
Other versions
DE69021192T2 (de
Inventor
Daniel Carteau
Philippe Schreck
Patricia Giacomini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Publication of DE69021192D1 publication Critical patent/DE69021192D1/de
Application granted granted Critical
Publication of DE69021192T2 publication Critical patent/DE69021192T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2089—Redundant storage control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G06F11/201—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media between storage system components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
DE69021192T 1990-03-08 1990-12-14 Peripheres Massenspeichersubsystem. Expired - Fee Related DE69021192T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9002962A FR2659460B1 (fr) 1990-03-08 1990-03-08 Sous-systeme peripherique de memoire de masse.

Publications (2)

Publication Number Publication Date
DE69021192D1 true DE69021192D1 (de) 1995-08-31
DE69021192T2 DE69021192T2 (de) 1995-12-07

Family

ID=9394530

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021192T Expired - Fee Related DE69021192T2 (de) 1990-03-08 1990-12-14 Peripheres Massenspeichersubsystem.

Country Status (5)

Country Link
US (1) US5325488A (de)
EP (1) EP0445479B1 (de)
JP (1) JPH06100957B2 (de)
DE (1) DE69021192T2 (de)
FR (1) FR2659460B1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3451099B2 (ja) 1991-12-06 2003-09-29 株式会社日立製作所 外部記憶サブシステム
US5420998A (en) * 1992-04-10 1995-05-30 Fujitsu Limited Dual memory disk drive
US5675816A (en) * 1992-05-26 1997-10-07 Fujitsu Limited Magnetic disk subsystem with failsafe battery charging and power shut down
JP3242407B2 (ja) * 1992-05-26 2001-12-25 富士通株式会社 磁気ディスク装置
US5504926A (en) * 1992-09-24 1996-04-02 Unisys Corporation Method for a host central processor and its associated controller to capture the selected one of a number of memory units via path control commands
JP3264465B2 (ja) 1993-06-30 2002-03-11 株式会社日立製作所 記憶システム
US5623699A (en) * 1994-12-06 1997-04-22 Thunderwave, Inc. Read only linear stream based cache system
US6061731A (en) * 1994-12-06 2000-05-09 Thunderwave, Inc. Read only linear stream based cache system
US5835102A (en) * 1995-10-19 1998-11-10 Sparta, Inc. System for transmission and recovery of digital data using video graphics display processor and method of operation thereof
US5751740A (en) * 1995-12-14 1998-05-12 Gorca Memory Systems Error detection and correction system for use with address translation memory controller
US5895485A (en) * 1997-02-24 1999-04-20 Eccs, Inc. Method and device using a redundant cache for preventing the loss of dirty data
US6330642B1 (en) * 2000-06-29 2001-12-11 Bull Hn Informatin Systems Inc. Three interconnected raid disk controller data processing system architecture
US7437490B2 (en) * 2005-05-27 2008-10-14 International Business Machines Corporation Channel communication array queues in hardware system area
DE102006003146B4 (de) * 2006-01-23 2016-05-12 Infineon Technologies Ag Vorrichtung und Verfahren zum Auslesen eines Datenwortes und Vorrichtung und Verfahren zum Speichern eines Datenblocks
WO2008097597A2 (en) * 2007-02-07 2008-08-14 General Dynamics Advanced Information Systems, Inc. Method and apparatus for a federated control plane in an orthogonal system
CN101556527B (zh) * 2008-04-10 2010-10-27 英业达股份有限公司 双备份存储器的磁盘连接层级的判断系统与方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868734A (en) * 1984-04-30 1989-09-19 Unisys Corp. Variable rate improvement of disc cache subsystem
FR2470412B1 (fr) * 1979-11-19 1986-10-03 Bull Sa Procede et dispositif de comptabilisation et de gestion des evenements asynchrones emis par des appareils peripheriques dans un systeme de traitement de donnees
US4931922A (en) * 1981-10-01 1990-06-05 Stratus Computer, Inc. Method and apparatus for monitoring peripheral device communications
US4780808A (en) * 1981-11-27 1988-10-25 Storage Technology Corporation Control of cache buffer for memory subsystem
US4535404A (en) * 1982-04-29 1985-08-13 Honeywell Information Systems Inc. Method and apparatus for addressing a peripheral interface by mapping into memory address space
US4600990A (en) * 1983-05-16 1986-07-15 Data General Corporation Apparatus for suspending a reserve operation in a disk drive
JPS6041145A (ja) * 1983-08-17 1985-03-04 Hitachi Ltd デイスクキヤツシユ装置
JPS617967A (ja) * 1984-06-15 1986-01-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Ｉ／ｏコントロ−ラ
JPS61243560A (ja) * 1985-04-19 1986-10-29 Yokogawa Electric Corp 二重化処理システム
US4747047A (en) * 1985-12-06 1988-05-24 Unisys Corporation Data transfer system using two peripheral controllers to access dual-ported data storage units
JPS63178360A (ja) * 1987-01-20 1988-07-22 Hitachi Ltd 入出力システム構成方式
US4821170A (en) * 1987-04-17 1989-04-11 Tandem Computers Incorporated Input/output system for multiprocessors
US4896266A (en) * 1987-06-03 1990-01-23 Bull Hn Information Systems Inc. Bus activity sequence controller
JPH0769882B2 (ja) * 1988-05-11 1995-07-31 富士通株式会社 クロスコール機能を有する入出力制御システム及びそのシステムにおける動的構成変更方法
US5038275A (en) * 1988-10-07 1991-08-06 Advanced Micro Devices, Inc. Status transfer structure within a data processing system with status read indication
US5133060A (en) * 1989-06-05 1992-07-21 Compuadd Corporation Disk controller includes cache memory and a local processor which limits data transfers from memory to cache in accordance with a maximum look ahead parameter

Also Published As

Publication number Publication date
JPH06100957B2 (ja) 1994-12-12
FR2659460B1 (fr) 1992-05-22
DE69021192T2 (de) 1995-12-07
EP0445479A1 (de) 1991-09-11
EP0445479B1 (de) 1995-07-26
JPH04219815A (ja) 1992-08-10
US5325488A (en) 1994-06-28
FR2659460A1 (fr) 1991-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee