DE3886182D1 - Mehrcachedatenspeicheranordnung. - Google Patents

Mehrcachedatenspeicheranordnung.

Info

Publication number
DE3886182D1
DE3886182D1 DE88309704T DE3886182T DE3886182D1 DE 3886182 D1 DE3886182 D1 DE 3886182D1 DE 88309704 T DE88309704 T DE 88309704T DE 3886182 T DE3886182 T DE 3886182T DE 3886182 D1 DE3886182 D1 DE 3886182D1
Authority
DE
Germany
Prior art keywords
storage device
data storage
cache data
cache
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88309704T
Other languages
English (en)
Other versions
DE3886182T2 (de
Inventor
David Paul Crane
Terence Michael Cole
Geoffrey Poskitt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of DE3886182D1 publication Critical patent/DE3886182D1/de
Application granted granted Critical
Publication of DE3886182T2 publication Critical patent/DE3886182T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE88309704T 1987-12-05 1988-10-17 Mehrcachedatenspeicheranordnung. Expired - Fee Related DE3886182T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB878728494A GB8728494D0 (en) 1987-12-05 1987-12-05 Multi-cache data storage system

Publications (2)

Publication Number Publication Date
DE3886182D1 true DE3886182D1 (de) 1994-01-20
DE3886182T2 DE3886182T2 (de) 1994-05-05

Family

ID=10628059

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88309704T Expired - Fee Related DE3886182T2 (de) 1987-12-05 1988-10-17 Mehrcachedatenspeicheranordnung.

Country Status (6)

Country Link
US (1) US5008813A (de)
EP (1) EP0320099B1 (de)
AU (1) AU609228B2 (de)
DE (1) DE3886182T2 (de)
GB (1) GB8728494D0 (de)
ZA (1) ZA888032B (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
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DE68917326T2 (de) 1988-01-20 1995-03-02 Advanced Micro Devices Inc Organisation eines integrierten Cachespeichers zur flexiblen Anwendung zur Unterstützung von Multiprozessor-Operationen.
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
US5535359A (en) * 1988-12-02 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Computer system with cache memory having address mask register
JPH0680499B2 (ja) * 1989-01-13 1994-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムのキャッシュ制御システムおよび方法
US5214777A (en) * 1989-03-27 1993-05-25 Ncr Corporation High speed read/modify/write memory system and method
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
FR2645987B1 (fr) * 1989-04-13 1991-06-07 Bull Sa Dispositif d'acceleration des acces memoire dans un systeme informatique
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5197146A (en) * 1989-06-21 1993-03-23 Hewlett-Packard Company Method for maintaining cache coherence in a multiprocessor computer system
US5155828A (en) * 1989-07-05 1992-10-13 Hewlett-Packard Company Computing system with a cache memory and an additional look-aside cache memory
JPH0340046A (ja) * 1989-07-06 1991-02-20 Hitachi Ltd キャッシュメモリ制御方式および情報処理装置
JP2511146B2 (ja) * 1989-07-07 1996-06-26 富士通株式会社 デ―タ処理装置
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
JPH0697449B2 (ja) * 1989-09-20 1994-11-30 株式会社日立製作所 多重化共有メモリ制御方法、多重化共有メモリシステムおよび共有メモリ拡張方法
JP2833062B2 (ja) * 1989-10-30 1998-12-09 株式会社日立製作所 キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置
US5297270A (en) * 1989-11-13 1994-03-22 Zenith Data Systems Corporation Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
US5263142A (en) * 1990-04-12 1993-11-16 Sun Microsystems, Inc. Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5249284A (en) * 1990-06-04 1993-09-28 Ncr Corporation Method and system for maintaining data coherency between main and cache memories
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
US5301340A (en) * 1990-10-31 1994-04-05 International Business Machines Corporation IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
GB2260429B (en) * 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US5469555A (en) * 1991-12-19 1995-11-21 Opti, Inc. Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
US5555382A (en) * 1992-04-24 1996-09-10 Digital Equipment Corporation Intelligent snoopy bus arbiter
US5778424A (en) * 1993-04-30 1998-07-07 Avsys Corporation Distributed placement, variable-size cache architecture
US5671391A (en) * 1994-01-10 1997-09-23 Ncr Corporation Coherent copyback protocol for multi-level cache memory systems
US6928521B1 (en) 2000-08-01 2005-08-09 International Business Machines Corporation Method, system, and data structures for using metadata in updating data in a storage device
US7681141B2 (en) * 2004-05-11 2010-03-16 Sony Computer Entertainment America Inc. Fast scrolling in a graphical user interface
JP4189402B2 (ja) * 2005-02-21 2008-12-03 パナソニック株式会社 キャッシュ回路
US7409524B2 (en) * 2005-08-17 2008-08-05 Hewlett-Packard Development Company, L.P. System and method for responding to TLB misses
US8806101B2 (en) * 2008-12-30 2014-08-12 Intel Corporation Metaphysical address space for holding lossy metadata in hardware
US9785462B2 (en) 2008-12-30 2017-10-10 Intel Corporation Registering a user-handler in hardware for transactional memory event handling
US8627014B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Memory model for hardware attributes within a transactional memory system
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
US10592424B2 (en) * 2017-07-14 2020-03-17 Arm Limited Range-based memory system

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US4453230A (en) * 1977-12-29 1984-06-05 Tokyo Shibaura Electric Co., Ltd. Address conversion system
US4445191A (en) * 1979-08-13 1984-04-24 Burroughs Corporation Data word handling enhancement in a page oriented named-data hierarchical memory system
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
US4785395A (en) * 1986-06-27 1988-11-15 Honeywell Bull Inc. Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
ATE160454T1 (de) * 1988-07-04 1997-12-15 Sun Microsystems Inc Multiprozessorsystem mit hierarchischer cachespeicheranordnung
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus

Also Published As

Publication number Publication date
ZA888032B (en) 1989-06-28
US5008813A (en) 1991-04-16
GB8728494D0 (en) 1988-01-13
EP0320099A2 (de) 1989-06-14
DE3886182T2 (de) 1994-05-05
AU2654188A (en) 1989-06-08
AU609228B2 (en) 1991-04-26
EP0320099B1 (de) 1993-12-08
EP0320099A3 (en) 1990-08-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee