ATE160454T1 - Multiprozessorsystem mit hierarchischer cachespeicheranordnung - Google Patents

Multiprozessorsystem mit hierarchischer cachespeicheranordnung

Info

Publication number
ATE160454T1
ATE160454T1 AT89907854T AT89907854T ATE160454T1 AT E160454 T1 ATE160454 T1 AT E160454T1 AT 89907854 T AT89907854 T AT 89907854T AT 89907854 T AT89907854 T AT 89907854T AT E160454 T1 ATE160454 T1 AT E160454T1
Authority
AT
Austria
Prior art keywords
data
computer system
buses
controllers
memory
Prior art date
Application number
AT89907854T
Other languages
English (en)
Inventor
Erik Hagersten
Seif Haridi
David H D Warren
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE8802495A external-priority patent/SE8802495D0/xx
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE160454T1 publication Critical patent/ATE160454T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
AT89907854T 1988-07-04 1989-06-29 Multiprozessorsystem mit hierarchischer cachespeicheranordnung ATE160454T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8802495A SE8802495D0 (sv) 1988-07-04 1988-07-04 Computer system
SE8804700A SE461813B (sv) 1988-07-04 1988-12-30 Multiprocessorarkitektur innefattande processor/minnespar sammankopplade med en eller flera bussar i ett hierarkiskt system

Publications (1)

Publication Number Publication Date
ATE160454T1 true ATE160454T1 (de) 1997-12-15

Family

ID=26660251

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89907854T ATE160454T1 (de) 1988-07-04 1989-06-29 Multiprozessorsystem mit hierarchischer cachespeicheranordnung

Country Status (5)

Country Link
EP (1) EP0424432B1 (de)
JP (1) JPH03505793A (de)
AT (1) ATE160454T1 (de)
DE (1) DE68928454T2 (de)
WO (1) WO1990000283A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8728494D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Multi-cache data storage system
US5341483A (en) * 1987-12-22 1994-08-23 Kendall Square Research Corporation Dynamic hierarchial associative memory
US5282201A (en) * 1987-12-22 1994-01-25 Kendall Square Research Corporation Dynamic packet routing network
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5251308A (en) * 1987-12-22 1993-10-05 Kendall Square Research Corporation Shared memory multiprocessor with data hiding and post-store
US5226039A (en) * 1987-12-22 1993-07-06 Kendall Square Research Corporation Packet routing switch
US5822578A (en) * 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
US5153595A (en) * 1990-03-26 1992-10-06 Geophysical Survey Systems, Inc. Range information from signal distortions
US5255388A (en) * 1990-09-26 1993-10-19 Honeywell Inc. Synchronizing slave processors through eavesdrop by one on a write request message directed to another followed by comparison of individual status request replies
US5202822A (en) * 1990-09-26 1993-04-13 Honeywell Inc. Universal scheme of input/output redundancy in a process control system
US5261092A (en) * 1990-09-26 1993-11-09 Honeywell Inc. Synchronizing slave processors through eavesdrop by one on periodic sync-verify messages directed to another followed by comparison of individual status
US5283126A (en) * 1991-08-29 1994-02-01 Bee Chemical Utilization of flexible coating on steel to impart superior scratch and chip resistance
CA2078312A1 (en) 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
JP2839060B2 (ja) * 1992-03-02 1998-12-16 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システムおよびデータ処理方法
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US6052762A (en) * 1996-12-02 2000-04-18 International Business Machines Corp. Method and apparatus for reducing system snoop latency
DE19703091A1 (de) * 1997-01-29 1998-07-30 Ppg Industries Inc Überzugsmittel für Nahrungsmittelbehälter
US5850628A (en) * 1997-01-30 1998-12-15 Hasbro, Inc. Speech and sound synthesizers with connected memories and outputs
CA2241909A1 (en) * 1997-07-10 1999-01-10 Howard Thomas Olnowich Cache coherent network, network adapter and message protocol for scalable shared memory processing systems
US6298419B1 (en) * 1998-03-26 2001-10-02 Compaq Computer Corporation Protocol for software distributed shared memory with memory scaling
WO2008085989A1 (en) 2007-01-10 2008-07-17 Richard Garfinkle A software method for data storage and retrieval
US20090150355A1 (en) * 2007-11-28 2009-06-11 Norton Garfinkle Software method for data storage and retrieval

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984002799A1 (en) * 1982-12-30 1984-07-19 Ibm A hierarchical memory system including separate cache memories for storing data and instructions
ATE62764T1 (de) * 1984-02-10 1991-05-15 Prime Computer Inc Cache-kohaerenz-anordnung.
EP0180369B1 (de) * 1984-10-31 1992-08-19 Texas Instruments Incorporated Durch beide, physikalische und virtuelle Addressen, addressierbarer Cache-Speicher
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method

Also Published As

Publication number Publication date
DE68928454D1 (de) 1998-01-02
JPH03505793A (ja) 1991-12-12
EP0424432A1 (de) 1991-05-02
DE68928454T2 (de) 1998-04-23
WO1990000283A1 (en) 1990-01-11
EP0424432B1 (de) 1997-11-19

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