DE68926761D1 - Mehrprozessorsystem mit einem mehranschlüssigen Cachespeicher - Google Patents

Mehrprozessorsystem mit einem mehranschlüssigen Cachespeicher

Info

Publication number
DE68926761D1
DE68926761D1 DE68926761T DE68926761T DE68926761D1 DE 68926761 D1 DE68926761 D1 DE 68926761D1 DE 68926761 T DE68926761 T DE 68926761T DE 68926761 T DE68926761 T DE 68926761T DE 68926761 D1 DE68926761 D1 DE 68926761D1
Authority
DE
Germany
Prior art keywords
processor system
port cache
cache
port
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68926761T
Other languages
English (en)
Other versions
DE68926761T2 (de
Inventor
Tadaaki Bandoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE68926761D1 publication Critical patent/DE68926761D1/de
Application granted granted Critical
Publication of DE68926761T2 publication Critical patent/DE68926761T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE68926761T 1988-05-06 1989-04-28 Mehrprozessorsystem mit einem mehranschlüssigen Cachespeicher Expired - Fee Related DE68926761T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63109045A JPH01280860A (ja) 1988-05-06 1988-05-06 マルチポートキヤツシユメモリを有するマルチプロセツサシステム

Publications (2)

Publication Number Publication Date
DE68926761D1 true DE68926761D1 (de) 1996-08-08
DE68926761T2 DE68926761T2 (de) 1996-11-28

Family

ID=14500210

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926761T Expired - Fee Related DE68926761T2 (de) 1988-05-06 1989-04-28 Mehrprozessorsystem mit einem mehranschlüssigen Cachespeicher

Country Status (5)

Country Link
EP (1) EP0340668B1 (de)
JP (1) JPH01280860A (de)
KR (1) KR960006499B1 (de)
CA (1) CA1323110C (de)
DE (1) DE68926761T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
JP2595753B2 (ja) * 1990-03-30 1997-04-02 日本電気株式会社 キャッシュメモリの無効化方式
JP2822588B2 (ja) * 1990-04-30 1998-11-11 日本電気株式会社 キャッシュメモリ装置
JPH0485788A (ja) * 1990-07-27 1992-03-18 Toshiba Corp 多ポートキャッシュメモリ
US5835945A (en) * 1990-08-06 1998-11-10 Ncr Corporation Memory system with write buffer, prefetch and internal caches
JPH04362755A (ja) * 1991-06-10 1992-12-15 Nec Corp 共用型拡張記憶試験方式
EP0552426A1 (de) * 1992-01-24 1993-07-28 International Business Machines Corporation Mehrstufiges Speichersystem
US6536664B2 (en) 1995-05-30 2003-03-25 Cashguard Ab Method for exchanging information between a cash register and a payment-processing device
JP3348367B2 (ja) * 1995-12-06 2002-11-20 富士通株式会社 多重アクセス方法および多重アクセスキャッシュメモリ装置
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
EP0999500A1 (de) * 1998-11-06 2000-05-10 Lucent Technologies Inc. Durch ein Anwendungsprogramm wiederkonfigurierbarer aufgeteilter Cache-Speicher
US6272567B1 (en) * 1998-11-24 2001-08-07 Nexabit Networks, Inc. System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed
DE102005037219A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle
DE102005037215A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle
US7600081B2 (en) * 2006-01-18 2009-10-06 Marvell World Trade Ltd. Processor architecture having multi-ported memory
JP2008097572A (ja) 2006-09-11 2008-04-24 Matsushita Electric Ind Co Ltd 演算装置、コンピュータシステム、および携帯機器
KR101635395B1 (ko) 2010-03-10 2016-07-01 삼성전자주식회사 멀티포트 데이터 캐시 장치 및 멀티포트 데이터 캐시 장치의 제어 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS537108B2 (de) * 1972-09-29 1978-03-14
JPS6037932B2 (ja) * 1980-07-29 1985-08-29 日本電気株式会社 キャッシュメモリ制御方式
JPS5858666A (ja) * 1981-10-02 1983-04-07 Hitachi Ltd デ−タ処理装置
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4489381A (en) * 1982-08-06 1984-12-18 International Business Machines Corporation Hierarchical memories having two ports at each subordinate memory level
JPS59213084A (ja) * 1983-05-16 1984-12-01 Fujitsu Ltd バッファ記憶装置のアクセス制御方式
JPS6041145A (ja) * 1983-08-17 1985-03-04 Hitachi Ltd デイスクキヤツシユ装置
JPS6388671A (ja) * 1986-10-01 1988-04-19 Nec Corp 同時並行処理制御方式
JPH0668735B2 (ja) * 1987-02-09 1994-08-31 日本電気アイシーマイコンシステム株式会社 キヤツシユメモリ−
JPS63257853A (ja) * 1987-04-03 1988-10-25 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン キヤツシユ・メモリ・システム

Also Published As

Publication number Publication date
EP0340668A2 (de) 1989-11-08
KR960006499B1 (ko) 1996-05-16
DE68926761T2 (de) 1996-11-28
JPH01280860A (ja) 1989-11-13
EP0340668A3 (en) 1990-08-29
CA1323110C (en) 1993-10-12
EP0340668B1 (de) 1996-07-03
KR890017615A (ko) 1989-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee