DE69130379T2 - Datenvorausladebefehl in einem Prozessor mit reduziertem Befehlssatz - Google Patents
Datenvorausladebefehl in einem Prozessor mit reduziertem BefehlssatzInfo
- Publication number
- DE69130379T2 DE69130379T2 DE69130379T DE69130379T DE69130379T2 DE 69130379 T2 DE69130379 T2 DE 69130379T2 DE 69130379 T DE69130379 T DE 69130379T DE 69130379 T DE69130379 T DE 69130379T DE 69130379 T2 DE69130379 T2 DE 69130379T2
- Authority
- DE
- Germany
- Prior art keywords
- processor
- instruction
- data preload
- instruction set
- reduced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000036316 preload Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/547,630 US5778423A (en) | 1990-06-29 | 1990-06-29 | Prefetch instruction for improving performance in reduced instruction set processor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69130379D1 DE69130379D1 (de) | 1998-11-26 |
DE69130379T2 true DE69130379T2 (de) | 1999-05-12 |
Family
ID=24185462
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69130379T Expired - Lifetime DE69130379T2 (de) | 1990-06-29 | 1991-06-28 | Datenvorausladebefehl in einem Prozessor mit reduziertem Befehlssatz |
Country Status (6)
Country | Link |
---|---|
US (1) | US5778423A (de) |
EP (1) | EP0463976B1 (de) |
JP (1) | JPH0695877A (de) |
KR (1) | KR100230105B1 (de) |
CA (1) | CA2045833A1 (de) |
DE (1) | DE69130379T2 (de) |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3590075B2 (ja) * | 1992-01-20 | 2004-11-17 | 株式会社東芝 | 仮想記憶方式のデータ処理装置及び方法 |
EP0636256B1 (de) * | 1992-03-31 | 1997-06-04 | Seiko Epson Corporation | Befehlsablauffolgeplanung von einem risc-superskalarprozessor |
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
DE69423206T2 (de) * | 1994-04-28 | 2000-09-07 | Hewlett Packard Co | Rechnervorrichtung mit Mitteln zum Erzwingen der Ausführung von Befehlen in regelmässiger Folge |
US5864707A (en) | 1995-12-11 | 1999-01-26 | Advanced Micro Devices, Inc. | Superscalar microprocessor configured to predict return addresses from a return stack storage |
JP3623840B2 (ja) | 1996-01-31 | 2005-02-23 | 株式会社ルネサステクノロジ | データ処理装置及びマイクロプロセッサ |
US5887159A (en) * | 1996-12-11 | 1999-03-23 | Digital Equipment Corporation | Dynamically determining instruction hint fields |
US6195735B1 (en) * | 1996-12-31 | 2001-02-27 | Texas Instruments Incorporated | Prefetch circuity for prefetching variable size data |
US6490658B1 (en) * | 1997-06-23 | 2002-12-03 | Sun Microsystems, Inc. | Data prefetch technique using prefetch cache, micro-TLB, and history file |
US6175898B1 (en) * | 1997-06-23 | 2001-01-16 | Sun Microsystems, Inc. | Method for prefetching data using a micro-TLB |
KR19990049284A (ko) * | 1997-12-12 | 1999-07-05 | 구본준 | 데이터 프로그램 장치 |
US5948095A (en) * | 1997-12-31 | 1999-09-07 | Intel Corporation | Method and apparatus for prefetching data in a computer system |
US6141734A (en) * | 1998-02-03 | 2000-10-31 | Compaq Computer Corporation | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol |
JPH11259437A (ja) * | 1998-03-12 | 1999-09-24 | Hitachi Ltd | 不要バリア命令の削減方式 |
US6088789A (en) * | 1998-05-13 | 2000-07-11 | Advanced Micro Devices, Inc. | Prefetch instruction specifying destination functional unit and read/write access mode |
US6401196B1 (en) * | 1998-06-19 | 2002-06-04 | Motorola, Inc. | Data processor system having branch control and method thereof |
US6526481B1 (en) | 1998-12-17 | 2003-02-25 | Massachusetts Institute Of Technology | Adaptive cache coherence protocols |
US6636950B1 (en) | 1998-12-17 | 2003-10-21 | Massachusetts Institute Of Technology | Computer architecture for shared memory access |
US6308322B1 (en) * | 1999-04-06 | 2001-10-23 | Hewlett-Packard Company | Method and apparatus for reduction of indirect branch instruction overhead through use of target address hints |
US6470444B1 (en) * | 1999-06-16 | 2002-10-22 | Intel Corporation | Method and apparatus for dividing a store operation into pre-fetch and store micro-operations |
US6453389B1 (en) * | 1999-06-25 | 2002-09-17 | Hewlett-Packard Company | Optimizing computer performance by using data compression principles to minimize a loss function |
US6421762B1 (en) | 1999-06-30 | 2002-07-16 | International Business Machines Corporation | Cache allocation policy based on speculative request history |
US6532521B1 (en) | 1999-06-30 | 2003-03-11 | International Business Machines Corporation | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy |
US6393528B1 (en) * | 1999-06-30 | 2002-05-21 | International Business Machines Corporation | Optimized cache allocation algorithm for multiple speculative requests |
US6510494B1 (en) | 1999-06-30 | 2003-01-21 | International Business Machines Corporation | Time based mechanism for cached speculative data deallocation |
US6360299B1 (en) * | 1999-06-30 | 2002-03-19 | International Business Machines Corporation | Extended cache state with prefetched stream ID information |
US6421763B1 (en) | 1999-06-30 | 2002-07-16 | International Business Machines Corporation | Method for instruction extensions for a tightly coupled speculative request unit |
US6496921B1 (en) | 1999-06-30 | 2002-12-17 | International Business Machines Corporation | Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions |
DE19948100A1 (de) * | 1999-10-06 | 2001-04-12 | Infineon Technologies Ag | Prozessorsystem |
WO2001025900A1 (en) | 1999-10-06 | 2001-04-12 | Cradle Technologies | Risc processor using register codes for expanded instruction set |
WO2001025941A1 (en) | 1999-10-06 | 2001-04-12 | Cradle Technologies | Multiprocessor computer systems with command fifo buffer at each target device |
US6604188B1 (en) | 1999-10-20 | 2003-08-05 | Transmeta Corporation | Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction |
US6728865B1 (en) | 1999-10-20 | 2004-04-27 | Transmeta Corporation | Pipeline replay support for unaligned memory operations |
US7032100B1 (en) * | 1999-12-17 | 2006-04-18 | Koninklijke Philips Electronics N.V. | Simple algorithmic cryptography engine |
US7058793B1 (en) * | 1999-12-20 | 2006-06-06 | Unisys Corporation | Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline |
US6728873B1 (en) * | 2000-06-06 | 2004-04-27 | International Business Machines Corporation | System and method for providing multiprocessor speculation within a speculative branch path |
US6615300B1 (en) | 2000-06-19 | 2003-09-02 | Transmeta Corporation | Fast look-up of indirect branch destination in a dynamic translation system |
US6675280B2 (en) | 2001-11-30 | 2004-01-06 | Intel Corporation | Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher |
US7260704B2 (en) | 2001-11-30 | 2007-08-21 | Intel Corporation | Method and apparatus for reinforcing a prefetch chain |
US6954840B2 (en) | 2001-11-30 | 2005-10-11 | Intel Corporation | Method and apparatus for content-aware prefetching |
US7093077B2 (en) | 2001-11-30 | 2006-08-15 | Intel Corporation | Method and apparatus for next-line prefetching from a predicted memory address |
CA2365375A1 (en) * | 2001-12-18 | 2003-06-18 | Ibm Canada Limited-Ibm Canada Limitee | Optimizing source code for iterative execution |
US6948053B2 (en) * | 2002-02-25 | 2005-09-20 | International Business Machines Corporation | Efficiently calculating a branch target address |
US20050278513A1 (en) * | 2004-05-19 | 2005-12-15 | Aris Aristodemou | Systems and methods of dynamic branch prediction in a microprocessor |
US7921250B2 (en) * | 2004-07-29 | 2011-04-05 | International Business Machines Corporation | Method to switch the lock-bits combination used to lock a page table entry upon receiving system reset exceptions |
US7243210B2 (en) * | 2005-05-31 | 2007-07-10 | Atmel Corporation | Extracted-index addressing of byte-addressable memories |
US20070074004A1 (en) | 2005-09-28 | 2007-03-29 | Arc International (Uk) Limited | Systems and methods for selectively decoupling a parallel extended instruction pipeline |
US20080091921A1 (en) * | 2006-10-12 | 2008-04-17 | Diab Abuaiadh | Data prefetching in a microprocessing environment |
US8185721B2 (en) * | 2008-03-04 | 2012-05-22 | Qualcomm Incorporated | Dual function adder for computing a hardware prefetch address and an arithmetic operation value |
GB2506902A (en) * | 2012-10-12 | 2014-04-16 | Ibm | Jump position and frame shifting in list based prefetching |
US9430392B2 (en) * | 2014-03-26 | 2016-08-30 | Intel Corporation | Supporting large pages in hardware prefetchers |
US10235176B2 (en) | 2015-12-17 | 2019-03-19 | The Charles Stark Draper Laboratory, Inc. | Techniques for metadata processing |
US10936713B2 (en) | 2015-12-17 | 2021-03-02 | The Charles Stark Draper Laboratory, Inc. | Techniques for metadata processing |
US20170286118A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Processors, methods, systems, and instructions to fetch data to indicated cache level with guaranteed completion |
US9672905B1 (en) * | 2016-07-22 | 2017-06-06 | Pure Storage, Inc. | Optimize data protection layouts based on distributed flash wear leveling |
US10565115B2 (en) | 2017-03-30 | 2020-02-18 | Western Digital Technologies, Inc. | Calculating the optimal number of LBNS to prefetch per CPU |
CN107203403B (zh) * | 2017-04-28 | 2020-08-07 | 李朝波 | 一种处理c语言switch/case语句的方法 |
US11150910B2 (en) | 2018-02-02 | 2021-10-19 | The Charles Stark Draper Laboratory, Inc. | Systems and methods for policy execution processing |
WO2019152792A1 (en) | 2018-02-02 | 2019-08-08 | Dover Microsystems, Inc. | Systems and methods for policy linking and/or loading for secure initialization |
WO2019213061A1 (en) | 2018-04-30 | 2019-11-07 | Dover Microsystems, Inc. | Systems and methods for checking safety properties |
TW202022679A (zh) | 2018-11-06 | 2020-06-16 | 美商多佛微系統公司 | 用於停滯主處理器的系統和方法 |
US11841956B2 (en) | 2018-12-18 | 2023-12-12 | Dover Microsystems, Inc. | Systems and methods for data lifecycle protection |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4161024A (en) * | 1977-12-22 | 1979-07-10 | Honeywell Information Systems Inc. | Private cache-to-CPU interface in a bus oriented data processing system |
JPS6057438A (ja) * | 1983-09-08 | 1985-04-03 | Hitachi Ltd | 仮想計算機システム制御装置 |
US4884197A (en) * | 1985-02-22 | 1989-11-28 | Intergraph Corporation | Method and apparatus for addressing a cache memory |
US4716545A (en) * | 1985-03-19 | 1987-12-29 | Wang Laboratories, Inc. | Memory means with multiple word read and single word write |
JPH02100740A (ja) * | 1988-10-07 | 1990-04-12 | Nec Corp | キャッシュ・メモリユニットのブロック・ロード動作方式 |
-
1990
- 1990-06-29 US US07/547,630 patent/US5778423A/en not_active Expired - Lifetime
-
1991
- 1991-06-27 CA CA002045833A patent/CA2045833A1/en not_active Abandoned
- 1991-06-28 KR KR1019910010881A patent/KR100230105B1/ko not_active IP Right Cessation
- 1991-06-28 EP EP91401782A patent/EP0463976B1/de not_active Expired - Lifetime
- 1991-06-28 JP JP3254073A patent/JPH0695877A/ja active Pending
- 1991-06-28 DE DE69130379T patent/DE69130379T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0463976B1 (de) | 1998-10-21 |
JPH0695877A (ja) | 1994-04-08 |
KR920001322A (ko) | 1992-01-30 |
KR100230105B1 (ko) | 1999-11-15 |
US5778423A (en) | 1998-07-07 |
DE69130379D1 (de) | 1998-11-26 |
EP0463976A3 (en) | 1993-08-25 |
EP0463976A2 (de) | 1992-01-02 |
CA2045833A1 (en) | 1991-12-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN |