DE69129872D1 - Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher - Google Patents

Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher

Info

Publication number
DE69129872D1
DE69129872D1 DE69129872T DE69129872T DE69129872D1 DE 69129872 D1 DE69129872 D1 DE 69129872D1 DE 69129872 T DE69129872 T DE 69129872T DE 69129872 T DE69129872 T DE 69129872T DE 69129872 D1 DE69129872 D1 DE 69129872D1
Authority
DE
Germany
Prior art keywords
performance
data processing
processing system
instruction cache
enhancing instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69129872T
Other languages
English (en)
Other versions
DE69129872T2 (de
Inventor
Chi-Hung Chi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69129872D1 publication Critical patent/DE69129872D1/de
Publication of DE69129872T2 publication Critical patent/DE69129872T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
DE69129872T 1990-03-27 1991-03-25 Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher Expired - Lifetime DE69129872T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US50061290A 1990-03-27 1990-03-27

Publications (2)

Publication Number Publication Date
DE69129872D1 true DE69129872D1 (de) 1998-09-03
DE69129872T2 DE69129872T2 (de) 1999-03-04

Family

ID=23990184

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129872T Expired - Lifetime DE69129872T2 (de) 1990-03-27 1991-03-25 Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher

Country Status (4)

Country Link
US (1) US5701435A (de)
EP (1) EP0449369B1 (de)
JP (1) JP3095802B2 (de)
DE (1) DE69129872T2 (de)

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US5951679A (en) * 1996-10-31 1999-09-14 Texas Instruments Incorporated Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle
US5958045A (en) * 1997-04-02 1999-09-28 Advanced Micro Devices, Inc. Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
DE19747275A1 (de) * 1997-10-25 1999-04-29 Philips Patentverwaltung Mobilfunkgerät mit einem Steuersignalgenerator
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6393527B1 (en) * 1998-12-18 2002-05-21 Ati International Srl Prefetch buffer with continue detect
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US6748496B1 (en) * 2000-04-18 2004-06-08 Ati International Srl Method and apparatus for providing cacheable data to a peripheral device
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
WO2002061574A1 (en) 2001-01-30 2002-08-08 Koninklijke Philips Electronics N.V. Computer instruction with instruction fetch control bits
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US6925535B2 (en) * 2001-08-29 2005-08-02 Hewlett-Packard Development Company, L.P. Program control flow conditioned on presence of requested data in cache memory
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7055000B1 (en) 2003-08-29 2006-05-30 Western Digital Technologies, Inc. Disk drive employing enhanced instruction cache management to facilitate non-sequential immediate operands
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
JP4837247B2 (ja) * 2003-09-24 2011-12-14 パナソニック株式会社 プロセッサ
US7917731B2 (en) * 2006-08-02 2011-03-29 Qualcomm Incorporated Method and apparatus for prefetching non-sequential instruction addresses
EP1901169A1 (de) * 2006-09-14 2008-03-19 SiTel Semiconductor B.V. Anordnung mit Befehlscache
US9311085B2 (en) * 2007-12-30 2016-04-12 Intel Corporation Compiler assisted low power and high performance load handling based on load types
US8312442B2 (en) * 2008-12-10 2012-11-13 Oracle America, Inc. Method and system for interprocedural prefetching
JP5444889B2 (ja) * 2009-06-30 2014-03-19 富士通株式会社 演算処理装置および演算処理装置の制御方法
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US9772824B2 (en) * 2015-03-25 2017-09-26 International Business Machines Corporation Program structure-based blocking
US11650821B1 (en) * 2021-05-19 2023-05-16 Xilinx, Inc. Branch stall elimination in pipelined microprocessors

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US3466613A (en) * 1967-01-13 1969-09-09 Ibm Instruction buffering system
US4157587A (en) * 1977-12-22 1979-06-05 Honeywell Information Systems Inc. High speed buffer memory system with word prefetch
US4189770A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Cache bypass control for operand fetches
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
US4500954A (en) * 1981-10-15 1985-02-19 International Business Machines Corporation Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass
US4594659A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Method and apparatus for prefetching instructions for a central execution pipeline unit
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4807110A (en) * 1984-04-06 1989-02-21 International Business Machines Corporation Prefetching system for a cache having a second directory for sequentially accessed blocks
US4942518A (en) * 1984-06-20 1990-07-17 Convex Computer Corporation Cache store bypass for computer
JPH0630075B2 (ja) * 1984-08-31 1994-04-20 株式会社日立製作所 キャッシュメモリを有するデータ処理装置
US4691277A (en) * 1984-10-24 1987-09-01 International Business Machines Corp. Small instruction cache using branch target table to effect instruction prefetch
US4761731A (en) * 1985-08-14 1988-08-02 Control Data Corporation Look-ahead instruction fetch control for a cache memory
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
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US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
US4860197A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Branch cache system with instruction boundary determination independent of parcel boundary
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
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US4876642A (en) * 1988-01-19 1989-10-24 Gibson Glenn A Rules and apparatus for a loop capturing code buffer that prefetches instructions
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US5099419A (en) * 1988-11-25 1992-03-24 Nec Corporation Pipeline microcomputer having branch instruction detector and bus controller for producing and carrying branch destination address prior to instruction execution

Also Published As

Publication number Publication date
US5701435A (en) 1997-12-23
EP0449369B1 (de) 1998-07-29
EP0449369A3 (en) 1992-03-18
EP0449369A2 (de) 1991-10-02
DE69129872T2 (de) 1999-03-04
JP3095802B2 (ja) 2000-10-10
JPH04225428A (ja) 1992-08-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL