JPH04501027A - キャッシュメモリー付マルチ処理システム - Google Patents
キャッシュメモリー付マルチ処理システムInfo
- Publication number
- JPH04501027A JPH04501027A JP1507645A JP50764589A JPH04501027A JP H04501027 A JPH04501027 A JP H04501027A JP 1507645 A JP1507645 A JP 1507645A JP 50764589 A JP50764589 A JP 50764589A JP H04501027 A JPH04501027 A JP H04501027A
- Authority
- JP
- Japan
- Prior art keywords
- data
- cache
- bus
- main memory
- memory means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (12)
- 1.中央処理ユニットと,主メモリー手段と,バス手段とを含むデータ処理シス テムにおいて, 該中央処理ユニットとバス手段との間に結合され主メモリー手段から受けたデー タユニットをアドレス可能記憶位置内に記憶するキャッシュメモリー手段であっ て, データユニットの無効姓を示す装置を有しないキャッシュメモリー手段,各デー タユニット記憶位置に関連し,該位置の内容が主メモリー手段から受信されてか ら修正されたか否かを示すステータス手段,キャッシュメモリー手段に関連し, データユニットが中央処理ユニットから要求された時に各データユニットが最新 のデータを代表することを確認する制御手段とを含むことを特徴とするデータ処 理システム。
- 2.前記ステータス手段が,データユニット記憶位置の内容が他にあるか否かを 示す場合に,中央処理ユニットから受けたデータユニットをキャッシュメモリー ユニットのデータユニット記憶位置に入れる手段を含み,前記制御手段は入力し たデータユニットが他にあることのステータス手段の表示に応答して入力したデ ータユニットを主メモリー手段に送信させることを特徴とする請求項1記載のデ ータ処理システム。
- 3.前記制御手段は,データユニットの主メモリー手段への送信に応答してステ ータス手段を修正してキャッシュメモリー手段内の記憶位置内のデータユニット が主メモリー手段内に記憶されるデータユニットと相違しないことを示すことを 特徴とする請求項2記載のデータ処理システム。
- 4.前記キャッシュメモリー手段に関連しかつバス手段に結合され,主メモリー 手段に書込まれたデータユニットを監視してデータユニットを主メモリー手段か ら移送する監視手段を更に含むことを特徴とする請求項3記載のデータ処理シス テム。
- 5.主メモリー手段に対してマルチデータ読出し表示を発生させるキャッシュコ ントローラ手段, 前記ステータス手段がキャッシュメモリー手段の記憶位置内のデータユニットか 主メモリー手段から最近に書戻されたため内容物が修正されていると表示した時 に主メモリー手段からデータユニットをキャッシュメモリー手段に記憶位置への 移送を禁止するレジスタ手段, とを含むことを特徴とする請求項1記載のデータ処理システム。
- 6.前記制御手段は断定された時に他から母線手段のアクセスを得るのを防ぐ保 持手段を含み,制御手段はメモリーに書込み指令に応答した後にキャッシュミス 及びダーティーデータを該指令に示すアドレスに発見した時に保持手段を断定す ることを特徴とする請求項1記載のデータ処理システム。
- 7.前記ダーティーデータが主メモリー手段に書込まれた後に制御手段によって 保持手段をリセットし,これによって主メモリー手段はアドレスデータを指令に よって指示されたキャッシュ手段のアドレスに書込むことを可能にすることを特 徴とする請求項6記載のデータ処理システム。
- 8.前記キャッシュメモリー手段に関連しかつバス手段に接続され,バス手段に 主メモリー手段からデータレジスタに移送されたデータのアドレスを検出するバ ス監視手段, 移送されたデータと同じアドレスを有するデータがキャッシュメモリー手段内に あるか否かを定め存在すれば保持信号をバス手段に発生する手段,とを含むこと を特徴とする請求項1記載のデータ処理システム。
- 9.キャッシュメモリー手段内のアドレスに記憶されたデータが移送されたデー タと相違するか否かを検出し,この場合に相違する内容のデータをキャッシュメ モリー手段からデータレジスタに移送する手段をさらに含むことを特徴とする請 求項8記載のデータ処理システム。
- 10.前記データレジスタは保持信号の感知に応答して母線手段との相互作用を 保ち,異なる内容のデータをキャッシュメモリー手段から受けることを特徴とす る請求項9記載のデータ処理システム。
- 11.マルチデータユニット移送レジスタと,主メモリーからの母線手段への多 数データ読出しの検出に応答してこのデータユニットがキャッシュメモリー手段 内にあるか否かを定める手段をさらに含み,マルチデータユニット移送レジスタ 内の存在の表示を記録し,データユニットがダーティーであるか否かを定めるこ とを特徴とする請求項10記載のデータ処理システム。
- 12.更に指示されたデータユニットがキャッシュレジスタ内に存在しダーティ ーである場合にキャッシュメモリー手段からマルチデータユニット移送の受取者 に移送する手段を含むことを特徴とする請求項11記載のデータ処理システム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US213,556 | 1988-06-30 | ||
US07/213,556 US4939641A (en) | 1988-06-30 | 1988-06-30 | Multi-processor system with cache memories |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001307304A Division JP2002163148A (ja) | 1988-06-30 | 2001-10-03 | キャッシュメモリー付マルチ処理システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04501027A true JPH04501027A (ja) | 1992-02-20 |
JP3510240B2 JP3510240B2 (ja) | 2004-03-22 |
Family
ID=22795556
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50764589A Expired - Lifetime JP3510240B2 (ja) | 1988-06-30 | 1989-06-22 | キャッシュメモリー付マルチ処理システム |
JP2001307304A Pending JP2002163148A (ja) | 1988-06-30 | 2001-10-03 | キャッシュメモリー付マルチ処理システム |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001307304A Pending JP2002163148A (ja) | 1988-06-30 | 2001-10-03 | キャッシュメモリー付マルチ処理システム |
Country Status (7)
Country | Link |
---|---|
US (1) | US4939641A (ja) |
EP (1) | EP0422113B1 (ja) |
JP (2) | JP3510240B2 (ja) |
AU (1) | AU622471B2 (ja) |
CA (1) | CA1320284C (ja) |
DE (1) | DE68927172T2 (ja) |
WO (1) | WO1990000285A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8250309B2 (en) | 2004-02-16 | 2012-08-21 | Arm Limited | Control of data accesses to a cache in data processing |
Families Citing this family (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01302444A (ja) * | 1988-05-31 | 1989-12-06 | Toshiba Corp | 論理アドレスキャッシュ制御方式 |
US5148533A (en) * | 1989-01-05 | 1992-09-15 | Bull Hn Information Systems Inc. | Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units |
US5371874A (en) * | 1989-01-27 | 1994-12-06 | Digital Equipment Corporation | Write-read/write-pass memory subsystem cycle |
US5179679A (en) * | 1989-04-07 | 1993-01-12 | Shoemaker Kenneth D | Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss |
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US5155824A (en) * | 1989-05-15 | 1992-10-13 | Motorola, Inc. | System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address |
US5287484A (en) * | 1989-06-21 | 1994-02-15 | Hitachi, Ltd. | Multi-processor system for invalidating hierarchical cache |
JP2511146B2 (ja) * | 1989-07-07 | 1996-06-26 | 富士通株式会社 | デ―タ処理装置 |
US5283886A (en) * | 1989-08-11 | 1994-02-01 | Hitachi, Ltd. | Multiprocessor cache system having three states for generating invalidating signals upon write accesses |
CA2028085A1 (en) * | 1989-11-03 | 1991-05-04 | Dale J. Mayer | Paged memory controller |
DE69025302T2 (de) * | 1989-12-22 | 1996-10-02 | Digital Equipment Corp | Hochleistungsrasterpuffer- und -cachespeicheranordnung |
GB2239724B (en) * | 1990-01-05 | 1993-11-24 | Sun Microsystems Inc | Apparatus for maintaining consistency in a multi-processor computer system using virtual caching |
US5452463A (en) * | 1990-05-25 | 1995-09-19 | Dell Usa, L.P. | Processor and cache controller interface lock jumper |
US5249286A (en) * | 1990-05-29 | 1993-09-28 | National Semiconductor Corporation | Selectively locking memory locations within a microprocessor's on-chip cache |
US5249284A (en) * | 1990-06-04 | 1993-09-28 | Ncr Corporation | Method and system for maintaining data coherency between main and cache memories |
US5226150A (en) * | 1990-10-01 | 1993-07-06 | Digital Equipment Corporation | Apparatus for suppressing an error report from an address for which an error has already been reported |
US5339397A (en) * | 1990-10-12 | 1994-08-16 | International Business Machines Corporation | Hardware primary directory lock |
US5249282A (en) * | 1990-11-21 | 1993-09-28 | Benchmarq Microelectronics, Inc. | Integrated cache memory system with primary and secondary cache memories |
US5249283A (en) * | 1990-12-24 | 1993-09-28 | Ncr Corporation | Cache coherency method and apparatus for a multiple path interconnection network |
US5303362A (en) * | 1991-03-20 | 1994-04-12 | Digital Equipment Corporation | Coupled memory multiprocessor computer system including cache coherency management protocols |
JPH04328657A (ja) * | 1991-04-30 | 1992-11-17 | Toshiba Corp | キャッシュメモリ |
US5353423A (en) * | 1991-06-21 | 1994-10-04 | Compaq Computer Corporation | Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses |
US5440752A (en) * | 1991-07-08 | 1995-08-08 | Seiko Epson Corporation | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU |
GB2260429B (en) * | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5301298A (en) * | 1991-10-11 | 1994-04-05 | Intel Corporation | Processor for multiple cache coherent protocols |
US5584017A (en) * | 1991-12-19 | 1996-12-10 | Intel Corporation | Cache control which inhibits snoop cycles if processor accessing memory is the only processor allowed to cache the memory location |
EP0553743A1 (en) * | 1992-01-31 | 1993-08-04 | Motorola, Inc. | A cache controller |
EP0553742A1 (en) * | 1992-01-31 | 1993-08-04 | Motorola, Inc. | A method of operating a first and second cache tag memory array |
JPH06318174A (ja) * | 1992-04-29 | 1994-11-15 | Sun Microsyst Inc | キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法 |
GB2271201B (en) * | 1992-10-01 | 1995-12-13 | Digital Equipment Int | Low-overhead,non-coherent cache refreshment mechanism |
DE69327643T2 (de) * | 1992-12-18 | 2000-08-31 | Advanced Micro Devices Inc | Cachespeichersysteme |
US5682515A (en) * | 1993-01-25 | 1997-10-28 | Benchmarq Microelectronics, Inc. | Low power set associative cache memory with status inhibit of cache data output |
US5530832A (en) * | 1993-10-14 | 1996-06-25 | International Business Machines Corporation | System and method for practicing essential inclusion in a multiprocessor and cache hierarchy |
JP2634141B2 (ja) * | 1994-01-19 | 1997-07-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | マルチプロセッサ・システム |
JPH07248974A (ja) * | 1994-03-10 | 1995-09-26 | Hitachi Ltd | 情報処理装置 |
US5557769A (en) * | 1994-06-17 | 1996-09-17 | Advanced Micro Devices | Mechanism and protocol for maintaining cache coherency within an integrated processor |
US5548752A (en) * | 1994-08-10 | 1996-08-20 | Motorola, Inc. | Method and system for storing data in a memory device |
US6000017A (en) * | 1995-01-20 | 1999-12-07 | Intel Corporation | Hybrid tag architecture for a cache memory |
US5594863A (en) * | 1995-06-26 | 1997-01-14 | Novell, Inc. | Method and apparatus for network file recovery |
US5778431A (en) * | 1995-12-19 | 1998-07-07 | Advanced Micro Devices, Inc. | System and apparatus for partially flushing cache memory |
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US6021466A (en) * | 1996-03-14 | 2000-02-01 | Compaq Computer Corporation | Transferring data between caches in a multiple processor environment |
US5960456A (en) * | 1996-05-17 | 1999-09-28 | National Semiconductor Corporation | Method and apparatus for providing a readable and writable cache tag memory |
US5860113A (en) * | 1996-06-03 | 1999-01-12 | Opti Inc. | System for using a dirty bit with a cache memory |
US5937431A (en) * | 1996-07-12 | 1999-08-10 | Samsung Electronics Co., Ltd. | Multi- node, multi-level cache- only memory architecture with relaxed inclusion |
JP3590203B2 (ja) | 1996-07-16 | 2004-11-17 | 株式会社東芝 | 記憶手段の制御方法及びその装置 |
DE19654595A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US5900016A (en) * | 1997-04-02 | 1999-05-04 | Opti Inc. | System for using a cache memory with a write-back architecture |
JPH1173370A (ja) * | 1997-08-29 | 1999-03-16 | Fujitsu Ltd | 情報処理装置 |
US8686549B2 (en) * | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
JP4179677B2 (ja) | 1998-09-04 | 2008-11-12 | 株式会社ルネサステクノロジ | マルチプロセッサ装置 |
AU5805300A (en) * | 1999-06-10 | 2001-01-02 | Pact Informationstechnologie Gmbh | Sequence partitioning in cell structures |
EP1342158B1 (de) | 2000-06-13 | 2010-08-04 | Richter, Thomas | Pipeline ct-protokolle und -kommunikation |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) * | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
DE10392560D2 (de) | 2002-01-19 | 2005-05-12 | Pact Xpp Technologies Ag | Reconfigurierbarer Prozessor |
US8127061B2 (en) | 2002-02-18 | 2012-02-28 | Martin Vorbach | Bus systems and reconfiguration methods |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US20110161977A1 (en) * | 2002-03-21 | 2011-06-30 | Martin Vorbach | Method and device for data processing |
WO2004021176A2 (de) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Verfahren und vorrichtung zur datenverarbeitung |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
EP1537486A1 (de) | 2002-09-06 | 2005-06-08 | PACT XPP Technologies AG | Rekonfigurierbare sequenzerstruktur |
US8332592B2 (en) * | 2004-10-08 | 2012-12-11 | International Business Machines Corporation | Graphics processor with snoop filter |
US20070150658A1 (en) * | 2005-12-28 | 2007-06-28 | Jaideep Moses | Pinning locks in shared cache |
US8250503B2 (en) * | 2006-01-18 | 2012-08-21 | Martin Vorbach | Hardware definition method including determining whether to implement a function as hardware or software |
US8180968B2 (en) * | 2007-03-28 | 2012-05-15 | Oracle America, Inc. | Reduction of cache flush time using a dirty line limiter |
DE112008003643A5 (de) * | 2007-11-17 | 2010-10-28 | Krass, Maren | Rekonfigurierbare Fliesskomma- und Bit- ebenen Datenverarbeitungseinheit |
WO2009068014A2 (de) * | 2007-11-28 | 2009-06-04 | Pact Xpp Technologies Ag | Über datenverarbeitung |
US20110119657A1 (en) * | 2007-12-07 | 2011-05-19 | Martin Vorbach | Using function calls as compiler directives |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3735360A (en) * | 1971-08-25 | 1973-05-22 | Ibm | High speed buffer operation in a multi-processing system |
US3761883A (en) * | 1972-01-20 | 1973-09-25 | Ibm | Storage protect key array for a multiprocessing system |
US3845474A (en) * | 1973-11-05 | 1974-10-29 | Honeywell Inf Systems | Cache store clearing operation for multiprocessor mode |
US3967247A (en) * | 1974-11-11 | 1976-06-29 | Sperry Rand Corporation | Storage interface unit |
US4084234A (en) * | 1977-02-17 | 1978-04-11 | Honeywell Information Systems Inc. | Cache write capacity |
US4167782A (en) * | 1977-12-22 | 1979-09-11 | Honeywell Information Systems Inc. | Continuous updating of cache store |
US4394732A (en) * | 1980-11-14 | 1983-07-19 | Sperry Corporation | Cache/disk subsystem trickle |
US4464712A (en) * | 1981-07-06 | 1984-08-07 | International Business Machines Corporation | Second level cache replacement method and apparatus |
US4442487A (en) * | 1981-12-31 | 1984-04-10 | International Business Machines Corporation | Three level memory hierarchy using write and share flags |
US4551799A (en) * | 1983-02-28 | 1985-11-05 | Honeywell Information Systems Inc. | Verification of real page numbers of stack stored prefetched instructions from instruction cache |
US4527238A (en) * | 1983-02-28 | 1985-07-02 | Honeywell Information Systems Inc. | Cache with independent addressable data and directory arrays |
US4602368A (en) * | 1983-04-15 | 1986-07-22 | Honeywell Information Systems Inc. | Dual validity bit arrays |
JPS60138653A (ja) * | 1983-12-27 | 1985-07-23 | Hitachi Ltd | 階層記憶制御方式 |
US4685082A (en) * | 1985-02-22 | 1987-08-04 | Wang Laboratories, Inc. | Simplified cache with automatic update |
US4811209A (en) * | 1986-07-31 | 1989-03-07 | Hewlett-Packard Company | Cache memory with multiple valid bits for each data indication the validity within different contents |
-
1988
- 1988-06-30 US US07/213,556 patent/US4939641A/en not_active Expired - Lifetime
-
1989
- 1989-06-22 EP EP89908118A patent/EP0422113B1/en not_active Expired - Lifetime
- 1989-06-22 JP JP50764589A patent/JP3510240B2/ja not_active Expired - Lifetime
- 1989-06-22 WO PCT/US1989/002740 patent/WO1990000285A1/en active IP Right Grant
- 1989-06-22 DE DE68927172T patent/DE68927172T2/de not_active Expired - Lifetime
- 1989-06-22 AU AU39636/89A patent/AU622471B2/en not_active Expired
- 1989-06-27 CA CA000604069A patent/CA1320284C/en not_active Expired - Lifetime
-
2001
- 2001-10-03 JP JP2001307304A patent/JP2002163148A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8250309B2 (en) | 2004-02-16 | 2012-08-21 | Arm Limited | Control of data accesses to a cache in data processing |
Also Published As
Publication number | Publication date |
---|---|
EP0422113A4 (en) | 1992-03-25 |
DE68927172T2 (de) | 1997-04-24 |
CA1320284C (en) | 1993-07-13 |
EP0422113A1 (en) | 1991-04-17 |
DE68927172D1 (de) | 1996-10-17 |
US4939641A (en) | 1990-07-03 |
JP2002163148A (ja) | 2002-06-07 |
JP3510240B2 (ja) | 2004-03-22 |
AU3963689A (en) | 1990-01-23 |
WO1990000285A1 (en) | 1990-01-11 |
AU622471B2 (en) | 1992-04-09 |
EP0422113B1 (en) | 1996-09-11 |
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