DE68926410D1 - Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor - Google Patents

Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor

Info

Publication number
DE68926410D1
DE68926410D1 DE68926410T DE68926410T DE68926410D1 DE 68926410 D1 DE68926410 D1 DE 68926410D1 DE 68926410 T DE68926410 T DE 68926410T DE 68926410 T DE68926410 T DE 68926410T DE 68926410 D1 DE68926410 D1 DE 68926410D1
Authority
DE
Germany
Prior art keywords
control unit
same chip
parity control
microprocessor equipped
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68926410T
Other languages
English (en)
Other versions
DE68926410T2 (de
Inventor
Yoshikuni C O Nec Corpora Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE68926410D1 publication Critical patent/DE68926410D1/de
Application granted granted Critical
Publication of DE68926410T2 publication Critical patent/DE68926410T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
DE68926410T 1988-06-24 1989-06-23 Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor Expired - Fee Related DE68926410T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15732888 1988-06-24

Publications (2)

Publication Number Publication Date
DE68926410D1 true DE68926410D1 (de) 1996-06-13
DE68926410T2 DE68926410T2 (de) 1996-09-12

Family

ID=15647293

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926410T Expired - Fee Related DE68926410T2 (de) 1988-06-24 1989-06-23 Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor

Country Status (4)

Country Link
US (1) US5095485A (de)
EP (1) EP0348240B1 (de)
JP (1) JP2586138B2 (de)
DE (1) DE68926410T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418933A (en) * 1990-02-20 1995-05-23 Sharp Kabushiki Kaisha Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit
JP2719052B2 (ja) * 1991-02-21 1998-02-25 三菱電機株式会社 マイクロコンピュータ
KR940001593B1 (ko) * 1991-09-20 1994-02-25 삼성전자 주식회사 메인콘트롤러내에 내장한 버스콘트롤러 동작 시스템
DE4341082A1 (de) * 1993-12-02 1995-06-08 Teves Gmbh Alfred Schaltungsanordnung für sicherheitskritische Regelungssysteme
US5495579A (en) * 1994-03-25 1996-02-27 Bull Hn Information Systems Inc. Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count
US5515506A (en) * 1994-08-23 1996-05-07 Hewlett-Packard Company Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle
US5586129A (en) * 1994-11-29 1996-12-17 Brain Power Co. Parity bit memory simulator
US5737344A (en) * 1995-05-25 1998-04-07 International Business Machines Corporation Digital data storage with increased robustness against data loss
US5607458A (en) * 1995-07-13 1997-03-04 Pacesetter, Inc. Safety optimization in microprocessor controlled implantable devices
DE10018722A1 (de) * 1999-09-22 2001-03-29 Continental Teves Ag & Co Ohg Verfahren und Schaltungsanordnung zum Speichern von Datenworten in einem RAM Modul
EP1222545B1 (de) 1999-09-22 2010-10-27 Continental Teves AG & Co. oHG Verfahren und schaltungsanordnung zum speichern von datenworten in einem ram modul
KR101290865B1 (ko) * 2005-08-11 2013-07-29 콘티넨탈 테베스 아게 운트 코. 오하게 적어도 부분적으로 안전상-중대한 프로세스들을 제어 및/또는 조정하기 위한 마이크로프로세서 시스템
WO2009090502A1 (en) * 2008-01-16 2009-07-23 Freescale Semiconductor, Inc. Processor based system having ecc based check and access validation information means
US9542251B2 (en) * 2013-10-30 2017-01-10 Oracle International Corporation Error detection on a low pin count bus
US10599518B2 (en) 2015-12-31 2020-03-24 Texas Instruments Incorporated Protecting data memory in a signal processing system
KR20190046491A (ko) * 2017-10-26 2019-05-07 삼성전자주식회사 반도체 메모리, 반도체 메모리를 포함하는 메모리 시스템, 그리고 반도체 메모리의 동작 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection
JPS5833577B2 (ja) * 1977-03-17 1983-07-20 富士通株式会社 集積回路
JPS55105897A (en) * 1979-01-31 1980-08-13 Hitachi Koki Co Ltd Memory device
JPS56127246A (en) * 1980-03-10 1981-10-05 Hitachi Ltd Information processor
JPS58225446A (ja) * 1982-06-25 1983-12-27 Toshiba Corp メモリパリテイリトライ方式
US4528666A (en) * 1983-01-03 1985-07-09 Texas Instruments Incorporated Memory system with built in parity
JPS59161740A (ja) * 1983-02-28 1984-09-12 Fujitsu Ltd パリテイエラ−検出方式
US4625273A (en) * 1983-08-30 1986-11-25 Amdahl Corporation Apparatus for fast data storage with deferred error reporting
US4648034A (en) * 1984-08-27 1987-03-03 Zilog, Inc. Busy signal interface between master and slave processors in a computer system
JPS6170638A (ja) * 1984-09-13 1986-04-11 Toshiba Corp パリテイチエツク回路
JPS6194151A (ja) * 1984-10-12 1986-05-13 Nec Corp パリテイチエツク回路
JPS61163452A (ja) * 1985-01-11 1986-07-24 Nec Corp 中央制御装置
JPS61253550A (ja) * 1985-05-02 1986-11-11 Hitachi Micro Comput Eng Ltd デ−タ処理システム
US4670876A (en) * 1985-05-15 1987-06-02 Honeywell Inc. Parity integrity check logic
JPS6288040A (ja) * 1985-10-14 1987-04-22 Nec Corp マイクロプログラム制御装置
US4805173A (en) * 1986-09-15 1989-02-14 Thinking Machines Corporation Error control method and apparatus
JPS63124157A (ja) * 1986-11-14 1988-05-27 Hitachi Ltd プロセツサへのデ−タ取込方式
JPH0199133A (ja) * 1987-10-12 1989-04-18 Mitsubishi Electric Corp メモリパリテイ付マイクロプロセツサシステム

Also Published As

Publication number Publication date
US5095485A (en) 1992-03-10
EP0348240B1 (de) 1996-05-08
EP0348240A3 (de) 1991-04-10
JP2586138B2 (ja) 1997-02-26
EP0348240A2 (de) 1989-12-27
DE68926410T2 (de) 1996-09-12
JPH0277846A (ja) 1990-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee