DE68923112D1 - Mit einem Mikroprozessor verbundene Cachespeichersteuervorrichtung. - Google Patents

Mit einem Mikroprozessor verbundene Cachespeichersteuervorrichtung.

Info

Publication number
DE68923112D1
DE68923112D1 DE68923112T DE68923112T DE68923112D1 DE 68923112 D1 DE68923112 D1 DE 68923112D1 DE 68923112 T DE68923112 T DE 68923112T DE 68923112 T DE68923112 T DE 68923112T DE 68923112 D1 DE68923112 D1 DE 68923112D1
Authority
DE
Germany
Prior art keywords
microprocessor
control device
device connected
cache control
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923112T
Other languages
English (en)
Other versions
DE68923112T2 (de
Inventor
Eiji C O Nec Corporat Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE68923112D1 publication Critical patent/DE68923112D1/de
Publication of DE68923112T2 publication Critical patent/DE68923112T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
DE68923112T 1988-04-12 1989-04-11 Mit einem Mikroprozessor verbundene Cachespeichersteuervorrichtung. Expired - Fee Related DE68923112T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9051088 1988-04-12

Publications (2)

Publication Number Publication Date
DE68923112D1 true DE68923112D1 (de) 1995-07-27
DE68923112T2 DE68923112T2 (de) 1995-11-30

Family

ID=14000472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923112T Expired - Fee Related DE68923112T2 (de) 1988-04-12 1989-04-11 Mit einem Mikroprozessor verbundene Cachespeichersteuervorrichtung.

Country Status (3)

Country Link
US (1) US5014188A (de)
EP (1) EP0337385B1 (de)
DE (1) DE68923112T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255378A (en) * 1989-04-05 1993-10-19 Intel Corporation Method of transferring burst data in a microprocessor
GB8915422D0 (en) * 1989-07-05 1989-08-23 Apricot Computers Plc Computer with cache
JP2509344B2 (ja) * 1989-09-19 1996-06-19 富士通株式会社 デ―タ処理装置
US5625793A (en) * 1991-04-15 1997-04-29 International Business Machines Corporation Automatic cache bypass for instructions exhibiting poor cache hit ratio
US5325515A (en) * 1991-05-14 1994-06-28 Nec Electronics, Inc. Single-component memory controller utilizing asynchronous state machines
US6223264B1 (en) * 1991-10-24 2001-04-24 Texas Instruments Incorporated Synchronous dynamic random access memory and data processing system using an address select signal
US5802548A (en) * 1991-10-25 1998-09-01 Chips And Technologies, Inc. Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers
US5519872A (en) * 1993-12-30 1996-05-21 Intel Corporation Fast address latch with automatic address incrementing
JP2704113B2 (ja) * 1994-04-26 1998-01-26 日本電気アイシーマイコンシステム株式会社 データ処理装置
US5566318A (en) * 1994-08-02 1996-10-15 Ramtron International Corporation Circuit with a single address register that augments a memory controller by enabling cache reads and page-mode writes
JP3153078B2 (ja) * 1994-09-09 2001-04-03 日本電気株式会社 データ処理装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910656A (en) * 1987-09-21 1990-03-20 Motorola, Inc. Bus master having selective burst initiation
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
US4912630A (en) * 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control

Also Published As

Publication number Publication date
EP0337385A2 (de) 1989-10-18
DE68923112T2 (de) 1995-11-30
US5014188A (en) 1991-05-07
EP0337385B1 (de) 1995-06-21
EP0337385A3 (de) 1991-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee