DE68928452D1 - Unterbrechungssteuerung - Google Patents

Unterbrechungssteuerung

Info

Publication number
DE68928452D1
DE68928452D1 DE68928452T DE68928452T DE68928452D1 DE 68928452 D1 DE68928452 D1 DE 68928452D1 DE 68928452 T DE68928452 T DE 68928452T DE 68928452 T DE68928452 T DE 68928452T DE 68928452 D1 DE68928452 D1 DE 68928452D1
Authority
DE
Germany
Prior art keywords
interrupt control
interrupt
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928452T
Other languages
English (en)
Other versions
DE68928452T2 (de
Inventor
Takashi Miyamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68928452D1 publication Critical patent/DE68928452D1/de
Application granted granted Critical
Publication of DE68928452T2 publication Critical patent/DE68928452T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE68928452T 1988-09-05 1989-09-05 Unterbrechungssteuerung Expired - Fee Related DE68928452T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63220540A JPH0268632A (ja) 1988-09-05 1988-09-05 割込み制御装置

Publications (2)

Publication Number Publication Date
DE68928452D1 true DE68928452D1 (de) 1998-01-02
DE68928452T2 DE68928452T2 (de) 1998-04-09

Family

ID=16752592

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928452T Expired - Fee Related DE68928452T2 (de) 1988-09-05 1989-09-05 Unterbrechungssteuerung

Country Status (5)

Country Link
US (1) US5133056A (de)
EP (1) EP0358163B1 (de)
JP (1) JPH0268632A (de)
KR (1) KR920004403B1 (de)
DE (1) DE68928452T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261107A (en) * 1989-11-03 1993-11-09 International Business Machines Corp. Programable interrupt controller
JPH0743653B2 (ja) * 1990-07-25 1995-05-15 株式会社東芝 割込みコントローラ
US5282272A (en) * 1990-12-21 1994-01-25 Intel Corporation Interrupt distribution scheme for a computer bus
US5805841A (en) * 1991-07-24 1998-09-08 Micron Electronics, Inc. Symmetric parallel multi-processing bus architeture
EP0535821B1 (de) * 1991-09-27 1997-11-26 Sun Microsystems, Inc. Verfahren und Gerät für die dynamische Zuweisung von unadressierten Unterbrechungen
US5404535A (en) * 1991-10-22 1995-04-04 Bull Hn Information Systems Inc. Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system
EP0619899B1 (de) * 1992-01-02 2000-07-19 Amdahl Corporation Anwendungs-software für hardware-unterbrechungen.
JPH05233318A (ja) * 1992-02-18 1993-09-10 Nec Corp マイクロプロセッサ
US5369769A (en) * 1992-09-09 1994-11-29 Intel Corporation Method and circuitry for selecting a free interrupt request level from a multiplicity of interrupt request levels in a personal computer system
US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
US5381552A (en) * 1993-04-26 1995-01-10 Ceridian Corporation Programmable system for prioritizing and collecting central processor unit interrupts
US5781187A (en) * 1994-05-31 1998-07-14 Advanced Micro Devices, Inc. Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system
GB9509626D0 (en) * 1995-05-12 1995-07-05 Sgs Thomson Microelectronics Processor interrupt control
KR0156173B1 (ko) * 1995-11-21 1998-11-16 문정환 인터럽트 발생회로
US5850555A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices, Inc. System and method for validating interrupts before presentation to a CPU
US5850558A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices System and method for referencing interrupt request information in a programmable interrupt controller
US5894578A (en) * 1995-12-19 1999-04-13 Advanced Micro Devices, Inc. System and method for using random access memory in a programmable interrupt controller
US5815733A (en) * 1996-02-01 1998-09-29 Apple Computer, Inc. System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits
JP3556465B2 (ja) * 1998-04-21 2004-08-18 株式会社ルネサステクノロジ 割り込みコントローラ
US6606677B1 (en) 2000-03-07 2003-08-12 International Business Machines Corporation High speed interrupt controller
DE10063936A1 (de) * 2000-12-20 2002-06-27 Thomson Brandt Gmbh Interrupt Controller für einen Mikroprozessor
US6988155B2 (en) * 2001-10-01 2006-01-17 International Business Machines Corporation Aggregation of hardware events in multi-node systems
GB2396445B (en) * 2002-12-19 2005-12-21 Advanced Risc Mach Ltd An interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources
US20060047878A1 (en) * 2004-08-25 2006-03-02 Zilavy Daniel V GPE register block
JP2008130056A (ja) * 2006-11-27 2008-06-05 Renesas Technology Corp 半導体回路
JP2010224689A (ja) * 2009-03-19 2010-10-07 Nec Soft Ltd デバイス制御システム、情報処理装置及びデバイス制御方法
JP2011076584A (ja) * 2009-09-02 2011-04-14 Renesas Electronics Corp 半導体集積回路装置
EP3644193A4 (de) * 2018-08-23 2020-11-25 Shenzhen Goodix Technology Co., Ltd. Unterbrechungsverarbeitungsverfahren, masterchip, slavechip und multichipsystem

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT988956B (it) * 1973-06-12 1975-04-30 Olivetti & Co Spa Governo multiplo
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
JPS5230353A (en) * 1975-09-04 1977-03-08 Nippon Telegr & Teleph Corp <Ntt> Micro program control method
US4023143A (en) * 1975-10-28 1977-05-10 Cincinnati Milacron Inc. Fixed priority interrupt control circuit
US4056847A (en) * 1976-08-04 1977-11-01 Rca Corporation Priority vector interrupt system
US4103327A (en) * 1977-03-18 1978-07-25 Bell Telephone Laboratories, Incorporated Interrupt control circuit
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
IT1100916B (it) * 1978-11-06 1985-09-28 Honeywell Inf Systems Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
JPS5999553A (ja) * 1982-11-29 1984-06-08 Nec Corp 割込制御方式
US4644467A (en) * 1982-12-29 1987-02-17 Mccarthy John M Multi-level dynamic priority selector groups of data elements
US4669057A (en) * 1983-10-03 1987-05-26 Honeywell Information Systems Inc. Data collection terminal interrupt structure
JPS6118059A (ja) * 1984-07-05 1986-01-25 Nec Corp メモリ回路
JPS6158037A (ja) * 1984-07-23 1986-03-25 Fujitsu Ltd サ−ビスプロセツサへの割り込み制御方式
US4701845A (en) * 1984-10-25 1987-10-20 Unisys Corporation User interface processor for computer network with maintenance and programmable interrupt capability
US4761732A (en) * 1985-11-29 1988-08-02 American Telephone And Telegraph Company, At&T Bell Laboratories Interrupt controller arrangement for mutually exclusive interrupt signals in data processing systems
US5003462A (en) * 1988-05-31 1991-03-26 International Business Machines Corporation Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means

Also Published As

Publication number Publication date
KR900005311A (ko) 1990-04-14
US5133056A (en) 1992-07-21
EP0358163A1 (de) 1990-03-14
EP0358163B1 (de) 1997-11-19
JPH0534699B2 (de) 1993-05-24
KR920004403B1 (ko) 1992-06-04
DE68928452T2 (de) 1998-04-09
JPH0268632A (ja) 1990-03-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee