DE69032145D1 - Schnittstellensteuerungssystem - Google Patents

Schnittstellensteuerungssystem

Info

Publication number
DE69032145D1
DE69032145D1 DE69032145T DE69032145T DE69032145D1 DE 69032145 D1 DE69032145 D1 DE 69032145D1 DE 69032145 T DE69032145 T DE 69032145T DE 69032145 T DE69032145 T DE 69032145T DE 69032145 D1 DE69032145 D1 DE 69032145D1
Authority
DE
Germany
Prior art keywords
control system
interface control
interface
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032145T
Other languages
English (en)
Other versions
DE69032145T2 (de
Inventor
Ray-Yuan Lan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wistron Corp
Acer Inc
Original Assignee
Acer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acer Inc filed Critical Acer Inc
Publication of DE69032145D1 publication Critical patent/DE69032145D1/de
Application granted granted Critical
Publication of DE69032145T2 publication Critical patent/DE69032145T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
DE69032145T 1989-09-12 1990-01-17 Schnittstellensteuerungssystem Expired - Fee Related DE69032145T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/405,986 US5235698A (en) 1989-09-12 1989-09-12 Bus interface synchronization control system

Publications (2)

Publication Number Publication Date
DE69032145D1 true DE69032145D1 (de) 1998-04-23
DE69032145T2 DE69032145T2 (de) 1998-11-19

Family

ID=23606057

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032145T Expired - Fee Related DE69032145T2 (de) 1989-09-12 1990-01-17 Schnittstellensteuerungssystem

Country Status (3)

Country Link
US (1) US5235698A (de)
EP (1) EP0417878B1 (de)
DE (1) DE69032145T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839664B2 (ja) * 1990-07-17 1998-12-16 株式会社東芝 計算機システム
US5412795A (en) * 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US5537582A (en) * 1993-05-21 1996-07-16 Draeger; Jeffrey S. Bus interface circuitry for synchronizing central processors running at multiple clock frequencies to other computer system circuitry
US5600824A (en) * 1994-02-04 1997-02-04 Hewlett-Packard Company Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer
US5802132A (en) * 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US5821784A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for generating 2/N mode bus clock signals
FR2751444B1 (fr) * 1996-07-18 1998-09-11 France Telecom Procede et dispositif de controle de la synchronisation temporelle entre une unite de traitement, par exemple un microprocesseur, et des moyens exterieurs
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US7831315B2 (en) * 2007-08-21 2010-11-09 Asm Japan K.K. Method for controlling semiconductor-processing apparatus
US7945345B2 (en) * 2008-08-06 2011-05-17 Asm Japan K.K. Semiconductor manufacturing apparatus
US10896106B2 (en) 2018-05-10 2021-01-19 Teradyne, Inc. Bus synchronization system that aggregates status

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5266346A (en) * 1975-11-29 1977-06-01 Tokyo Electric Co Ltd Synch. clock control of microcomputer system
US4241418A (en) * 1977-11-23 1980-12-23 Honeywell Information Systems Inc. Clock system having a dynamically selectable clock period
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4819164A (en) * 1983-12-12 1989-04-04 Texas Instruments Incorporated Variable frequency microprocessor clock generator
JPS63155340A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 記憶装置の読出し方式

Also Published As

Publication number Publication date
EP0417878B1 (de) 1998-03-18
EP0417878A3 (en) 1992-04-29
EP0417878A2 (de) 1991-03-20
US5235698A (en) 1993-08-10
DE69032145T2 (de) 1998-11-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ACER INC., HSIN CHU, TW

Owner name: WISTRON CORP., TAIPEH/T'AI-PEI, TW

8339 Ceased/non-payment of the annual fee