DE68918030D1 - Leseverstärker mit niedriger Leistung für eine programmierbare logische Einrichtung. - Google Patents

Leseverstärker mit niedriger Leistung für eine programmierbare logische Einrichtung.

Info

Publication number
DE68918030D1
DE68918030D1 DE68918030T DE68918030T DE68918030D1 DE 68918030 D1 DE68918030 D1 DE 68918030D1 DE 68918030 T DE68918030 T DE 68918030T DE 68918030 T DE68918030 T DE 68918030T DE 68918030 D1 DE68918030 D1 DE 68918030D1
Authority
DE
Germany
Prior art keywords
low power
programmable logic
sense amplifier
logic device
power sense
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918030T
Other languages
English (en)
Other versions
DE68918030T2 (de
Inventor
Jagdish Pathak
Hal Kurkowski
Stephen M Douglas
Dov-Ami Vider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of DE68918030D1 publication Critical patent/DE68918030D1/de
Application granted granted Critical
Publication of DE68918030T2 publication Critical patent/DE68918030T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
DE68918030T 1988-09-02 1989-07-24 Leseverstärker mit niedriger Leistung für eine programmierbare logische Einrichtung. Expired - Fee Related DE68918030T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/240,089 US4851720A (en) 1988-09-02 1988-09-02 Low power sense amplifier for programmable logic device

Publications (2)

Publication Number Publication Date
DE68918030D1 true DE68918030D1 (de) 1994-10-13
DE68918030T2 DE68918030T2 (de) 1995-05-18

Family

ID=22905076

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918030T Expired - Fee Related DE68918030T2 (de) 1988-09-02 1989-07-24 Leseverstärker mit niedriger Leistung für eine programmierbare logische Einrichtung.

Country Status (4)

Country Link
US (1) US4851720A (de)
EP (1) EP0357213B1 (de)
JP (1) JP2858134B2 (de)
DE (1) DE68918030T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793032B2 (ja) * 1989-04-27 1995-10-09 日本電気株式会社 半導体記憶装置
US4963769A (en) * 1989-05-08 1990-10-16 Cypress Semiconductor Circuit for selective power-down of unused circuitry
KR920001325B1 (ko) * 1989-06-10 1992-02-10 삼성전자 주식회사 메모리 소자내의 센스 앰프 드라이버
US5163168A (en) * 1990-03-30 1992-11-10 Matsushita Electric Industrial Co., Ltd. Pulse signal generator and redundancy selection signal generator
JP2789779B2 (ja) * 1990-04-14 1998-08-20 日本電気株式会社 メモリ装置
US5247213A (en) * 1990-05-08 1993-09-21 Advanced Micro Devices, Inc. Programmable sense amplifier power reduction
US5051620A (en) * 1990-07-31 1991-09-24 Burgin Kenneth N Precharged logic systems with protection against current leakage
US5450608A (en) * 1993-04-15 1995-09-12 Intel Corporation Programmable logic having selectable output states for initialization and resets asynchronously using control bit associated with each product term
US5572150A (en) * 1995-04-10 1996-11-05 International Business Machines Corporation Low power pre-discharged ratio logic
US5712790A (en) * 1995-04-11 1998-01-27 International Business Machines Corporation Method of power reduction in pla's
US5719505A (en) * 1995-04-11 1998-02-17 International Business Machines Corporation Reduced power PLA
US5565791A (en) * 1995-07-07 1996-10-15 Cypress Semiconductor Corporation Method and apparatus for disabling unused sense amplifiers
US5666310A (en) * 1996-01-30 1997-09-09 Cypress Semiconductor High-speed sense amplifier having variable current level trip point
JP3717388B2 (ja) * 2000-09-27 2005-11-16 株式会社リコー 基準電圧発生回路及びその出力値調整方法並びに電源装置
US7126869B1 (en) 2003-06-26 2006-10-24 Cypress Semiconductor Corp. Sense amplifier with dual cascode transistors and improved noise margin
US7400167B2 (en) * 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7505341B2 (en) * 2006-05-17 2009-03-17 Micron Technology, Inc. Low voltage sense amplifier and sensing method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
US4658158A (en) * 1980-07-03 1987-04-14 Xerox Corporation Voltage sense amplifier using NMOS
JPS57117188A (en) * 1981-01-12 1982-07-21 Toshiba Corp Sense amplifier circuit
DE3279855D1 (en) * 1981-12-29 1989-09-07 Fujitsu Ltd Nonvolatile semiconductor memory circuit
US4599525A (en) * 1983-02-02 1986-07-08 Rockwell International Corporation De-glitch circuitry for video game memories
JPS59181829A (ja) * 1983-03-31 1984-10-16 Toshiba Corp 半導体素子の出力バツフア回路
US4725984A (en) * 1984-02-21 1988-02-16 Seeq Technology, Inc. CMOS eprom sense amplifier
US4617479B1 (en) * 1984-05-03 1993-09-21 Altera Semiconductor Corp. Programmable logic array device using eprom technology
US4604732A (en) * 1984-05-29 1986-08-05 Thomson Components-Mostek Corporation Power supply dependent voltage reference circuit
US4609986A (en) * 1984-06-14 1986-09-02 Altera Corporation Programmable logic array device using EPROM technology
JPH0736273B2 (ja) * 1984-11-26 1995-04-19 株式会社日立製作所 半導体集積回路
JPH0793028B2 (ja) * 1984-12-22 1995-10-09 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
US4805150A (en) * 1984-12-25 1989-02-14 Kabushiki Kaisha Toshiba Programmable semiconductor memory device having grouped high voltage supply circuits for writing data
JPS621191A (ja) * 1985-03-11 1987-01-07 Nec Ic Microcomput Syst Ltd 信号出力回路
JPS6214520A (ja) * 1985-07-12 1987-01-23 Sony Corp メモリの出力バツフア回路
US4727519A (en) * 1985-11-25 1988-02-23 Motorola, Inc. Memory device including a clock generator with process tracking
JPS62197996A (ja) * 1986-02-24 1987-09-01 Toshiba Corp 半導体メモリのセンスアンプ
JPS62231500A (ja) * 1986-03-31 1987-10-12 Toshiba Corp 半導体記憶装置
FR2609831B1 (fr) * 1987-01-16 1989-03-31 Thomson Semiconducteurs Circuit de lecture pour memoire

Also Published As

Publication number Publication date
JPH02101699A (ja) 1990-04-13
EP0357213A3 (de) 1991-05-22
EP0357213A2 (de) 1990-03-07
DE68918030T2 (de) 1995-05-18
US4851720A (en) 1989-07-25
JP2858134B2 (ja) 1999-02-17
EP0357213B1 (de) 1994-09-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee