DE68915050D1 - Chipfreigabe-Eingangsschaltung in einer Halbleiterspeicheranordnung. - Google Patents

Chipfreigabe-Eingangsschaltung in einer Halbleiterspeicheranordnung.

Info

Publication number
DE68915050D1
DE68915050D1 DE68915050T DE68915050T DE68915050D1 DE 68915050 D1 DE68915050 D1 DE 68915050D1 DE 68915050 T DE68915050 T DE 68915050T DE 68915050 T DE68915050 T DE 68915050T DE 68915050 D1 DE68915050 D1 DE 68915050D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
input circuit
chip enable
enable input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915050T
Other languages
English (en)
Other versions
DE68915050T2 (de
Inventor
Hiroaki Intellectual Pr Tanaka
Naokazu Intellectual Miyawaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68915050D1 publication Critical patent/DE68915050D1/de
Application granted granted Critical
Publication of DE68915050T2 publication Critical patent/DE68915050T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE68915050T 1988-05-16 1989-05-16 Chipfreigabe-Eingangsschaltung in einer Halbleiterspeicheranordnung. Expired - Fee Related DE68915050T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63118468A JP2598081B2 (ja) 1988-05-16 1988-05-16 半導体メモリ

Publications (2)

Publication Number Publication Date
DE68915050D1 true DE68915050D1 (de) 1994-06-09
DE68915050T2 DE68915050T2 (de) 1994-09-29

Family

ID=14737417

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915050T Expired - Fee Related DE68915050T2 (de) 1988-05-16 1989-05-16 Chipfreigabe-Eingangsschaltung in einer Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4970694A (de)
EP (1) EP0342592B1 (de)
JP (1) JP2598081B2 (de)
KR (1) KR930000961B1 (de)
DE (1) DE68915050T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327392A (en) * 1989-01-13 1994-07-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise
JP2744115B2 (ja) * 1990-05-21 1998-04-28 株式会社東芝 疑似スタティックｒａｍの制御回路
US5144168A (en) * 1990-08-17 1992-09-01 Texas Instruments Incorporated Self latching input buffer
US5799186A (en) * 1990-12-20 1998-08-25 Eastman Kodak Company Method and apparatus for programming a peripheral processor with a serial output memory device
US5301165A (en) * 1992-10-28 1994-04-05 International Business Machines Corporation Chip select speedup circuit for a memory
JP2978794B2 (ja) * 1996-11-08 1999-11-15 日本電気アイシーマイコンシステム株式会社 半導体集積回路
KR100225954B1 (ko) * 1996-12-31 1999-10-15 김영환 전력 절감용 반도체 메모리 소자
JP2002124858A (ja) * 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
DE10047251C2 (de) * 2000-09-23 2002-10-17 Infineon Technologies Ag 1-aus-N-Decodierschaltung
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
RU2748727C2 (ru) 2017-01-31 2021-05-31 Хьюлетт-Паккард Дивелопмент Компани, Л.П. Доступ к блокам памяти в банке памяти

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538603A (en) * 1978-09-04 1980-03-18 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device
JPS5828676B2 (ja) * 1979-11-29 1983-06-17 富士通株式会社 デコ−ダ回路
JPS57171840A (en) * 1981-04-16 1982-10-22 Toshiba Corp Driving circuit
JPS5957525A (ja) * 1982-09-28 1984-04-03 Fujitsu Ltd Ｃｍｉｓ回路装置
JPS59207083A (ja) * 1983-05-10 1984-11-24 Nec Corp メモリ回路
JPS60193193A (ja) * 1984-03-13 1985-10-01 Toshiba Corp メモリｌｓｉ
US4665328A (en) * 1984-07-27 1987-05-12 National Semiconductor Corporation Multiple clock power down method and structure
JPS62202399A (ja) * 1985-10-04 1987-09-07 Mitsubishi Electric Corp 半導体メモリ
JPS63228494A (ja) * 1987-03-18 1988-09-22 Fujitsu Ltd ダイナミツク型デコ−ダ回路

Also Published As

Publication number Publication date
EP0342592A3 (de) 1992-02-19
EP0342592A2 (de) 1989-11-23
US4970694A (en) 1990-11-13
JP2598081B2 (ja) 1997-04-09
DE68915050T2 (de) 1994-09-29
JPH01287895A (ja) 1989-11-20
EP0342592B1 (de) 1994-05-04
KR930000961B1 (ko) 1993-02-11
KR890017702A (ko) 1989-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee