DE60335042D1 - Adaptives Zeitsystem zur Steuerung des Speicherzugriffs - Google Patents

Adaptives Zeitsystem zur Steuerung des Speicherzugriffs

Info

Publication number
DE60335042D1
DE60335042D1 DE60335042T DE60335042T DE60335042D1 DE 60335042 D1 DE60335042 D1 DE 60335042D1 DE 60335042 T DE60335042 T DE 60335042T DE 60335042 T DE60335042 T DE 60335042T DE 60335042 D1 DE60335042 D1 DE 60335042D1
Authority
DE
Germany
Prior art keywords
data source
memory access
latched
time system
delay clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60335042T
Other languages
English (en)
Inventor
Paul A Laberge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE60335042D1 publication Critical patent/DE60335042D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Static Random-Access Memory (AREA)
DE60335042T 2002-02-11 2003-01-29 Adaptives Zeitsystem zur Steuerung des Speicherzugriffs Expired - Lifetime DE60335042D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/073,611 US7076678B2 (en) 2002-02-11 2002-02-11 Method and apparatus for data transfer

Publications (1)

Publication Number Publication Date
DE60335042D1 true DE60335042D1 (de) 2010-12-30

Family

ID=27659717

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60305162T Expired - Lifetime DE60305162T2 (de) 2002-02-11 2003-01-29 Speicher und ein adaptives zeitsteuerungssystem zur steuerung des zugriffs auf den speicher
DE60335042T Expired - Lifetime DE60335042D1 (de) 2002-02-11 2003-01-29 Adaptives Zeitsystem zur Steuerung des Speicherzugriffs

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE60305162T Expired - Lifetime DE60305162T2 (de) 2002-02-11 2003-01-29 Speicher und ein adaptives zeitsteuerungssystem zur steuerung des zugriffs auf den speicher

Country Status (10)

Country Link
US (3) US7076678B2 (de)
EP (3) EP1679607B1 (de)
JP (1) JP3987038B2 (de)
KR (1) KR100733951B1 (de)
CN (1) CN100350402C (de)
AT (3) ATE326035T1 (de)
AU (1) AU2003205371A1 (de)
DE (2) DE60305162T2 (de)
TW (1) TWI257549B (de)
WO (1) WO2003069486A1 (de)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1446910B1 (de) 2001-10-22 2010-08-11 Rambus Inc. Phaseneinstellvorrichtung und verfahren für ein speicherbaustein-signalisierungssystem
US7076678B2 (en) * 2002-02-11 2006-07-11 Micron Technology, Inc. Method and apparatus for data transfer
US7139348B1 (en) * 2002-04-09 2006-11-21 Applied Micro Circuits Corporation Distributed clock network using all-digital master-slave delay lock loops
US7198197B2 (en) * 2002-11-05 2007-04-03 Rambus, Inc. Method and apparatus for data acquisition
US8675722B2 (en) * 2003-09-23 2014-03-18 International Business Machines Corporation Methods and apparatus for snapshot-based equalization of a communications channel
US7721060B2 (en) * 2003-11-13 2010-05-18 Intel Corporation Method and apparatus for maintaining data density for derived clocking
KR20050061123A (ko) * 2003-12-18 2005-06-22 삼성전자주식회사 Ｄｄｒ ｓｄｒａｍ 콘트롤러의 데이터 제어회로
US7178048B2 (en) * 2003-12-23 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for signal synchronization based on plural clock signals
DE102004013929B3 (de) * 2004-03-22 2005-08-11 Infineon Technologies Ag Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung
JP4904596B2 (ja) * 2004-12-03 2012-03-28 エスティー‐エリクソン、ソシエテ、アノニム ディジタル遅延線中のタップ位置の管理
US7596700B2 (en) * 2004-12-22 2009-09-29 Storage Technology Corporation Method and system for establishing trusting environment for sharing data between mutually mistrusting entities
US7587640B2 (en) * 2005-09-27 2009-09-08 Agere Systems Inc. Method and apparatus for monitoring and compensating for skew on a high speed parallel bus
US20080025448A1 (en) * 2006-07-27 2008-01-31 Marlin Viss Jitter characterization
US7876629B2 (en) * 2007-08-08 2011-01-25 Mediatek Inc. Memory control methods capable of dynamically adjusting sampling points, and related circuits
US7778093B2 (en) * 2007-08-08 2010-08-17 Mediatek Inc. Memory control circuit capable of dynamically adjusting deglitch windows, and related method
JP5172486B2 (ja) * 2008-06-12 2013-03-27 パナソニック株式会社 同期点検出方法及び通信装置
JP2010040092A (ja) * 2008-08-04 2010-02-18 Nec Electronics Corp 半導体集積回路
JP2010086246A (ja) * 2008-09-30 2010-04-15 Nec Electronics Corp メモリインターフェース及びメモリインターフェースの動作方法
JP2010086415A (ja) * 2008-10-01 2010-04-15 Panasonic Corp メモリインターフェース
TWI411976B (zh) * 2009-05-08 2013-10-11 Himax Tech Ltd 影像處理系統與取樣相位校正方法
JP5407551B2 (ja) * 2009-05-22 2014-02-05 富士通セミコンダクター株式会社 タイミング調整回路及びタイミング調整方法
US8037375B2 (en) * 2009-06-30 2011-10-11 Intel Corporation Fast data eye retraining for a memory
US8856578B2 (en) * 2010-08-20 2014-10-07 Fujitsu Semiconductor Limited Integrated circuit device including skew adjustment circuit and skew adjustment method
US9401225B2 (en) 2010-11-19 2016-07-26 Rambus Inc. Timing-drift calibration
US8645743B2 (en) * 2010-11-22 2014-02-04 Apple Inc. Mechanism for an efficient DLL training protocol during a frequency change
JP2012203515A (ja) 2011-03-24 2012-10-22 Toshiba Corp 半導体装置
US9824065B2 (en) 2012-01-06 2017-11-21 University Of New Hampshire Systems and methods for chaotic entanglement using cupolets
KR101977663B1 (ko) 2012-09-14 2019-05-13 삼성전자주식회사 임베디드 멀티미디어 카드 디바이스 및 그 동작방법
TWI483113B (zh) * 2012-10-29 2015-05-01 Hsiung Kuang Tsai 資料傳輸系統
KR101990974B1 (ko) * 2012-12-13 2019-06-19 삼성전자 주식회사 시스템-온 칩의 동작 방법 및 이를 포함하는 장치들
US20140281662A1 (en) * 2013-03-12 2014-09-18 Uniquify, Inc. Dynamically adaptive bit-leveling for data interfaces
US8947140B2 (en) 2013-03-12 2015-02-03 Uniquify, Inc. Continuous adaptive training for data interface timing calibration
BR112015019459B1 (pt) * 2013-03-15 2021-10-19 Intel Corporation Dispositivo para uso em um módulo de memória e método realizado em um módulo de memória
US9811273B1 (en) * 2014-12-23 2017-11-07 Cadence Design Systems, Inc. System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory
US10163508B2 (en) 2016-02-26 2018-12-25 Intel Corporation Supporting multiple memory types in a memory slot
US10083736B1 (en) * 2016-06-23 2018-09-25 Apple Inc. Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage
US10459855B2 (en) 2016-07-01 2019-10-29 Intel Corporation Load reduced nonvolatile memory interface
EP4328596A3 (de) 2017-11-15 2024-05-22 Proteantecs Ltd. Integrierte schaltungsmargenmessung und fehlervorhersagevorrichtung
US11391771B2 (en) 2017-11-23 2022-07-19 Proteantecs Ltd. Integrated circuit pad failure detection
US11740281B2 (en) 2018-01-08 2023-08-29 Proteantecs Ltd. Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing
EP3737953A4 (de) 2018-01-08 2021-10-13 Proteantecs Ltd. Integrierter arbeitslast-, temperatur- und/oder unterschwellenwertlecksensor für integrierte schaltung
TWI828676B (zh) 2018-04-16 2024-01-11 以色列商普騰泰克斯有限公司 用於積體電路剖析及異常檢測之方法和相關的電腦程式產品
US10395701B1 (en) * 2018-05-09 2019-08-27 Micron Technology, Inc. Memory device with a latching mechanism
CN112868016A (zh) 2018-06-19 2021-05-28 普罗泰克斯公司 高效集成电路模拟与测试
US11042301B2 (en) 2018-12-13 2021-06-22 Micron Technology, Inc. Host clock effective delay range extension
WO2020141516A1 (en) 2018-12-30 2020-07-09 Proteantecs Ltd. Integrated circuit i/o integrity and degradation monitoring
US11226752B2 (en) 2019-03-05 2022-01-18 Apple Inc. Filtering memory calibration
TW202127252A (zh) 2019-12-04 2021-07-16 以色列商普騰泰克斯有限公司 記憶體裝置退化偵測
CN111208867B (zh) * 2019-12-27 2021-08-24 芯创智（北京）微电子有限公司 一种基于ddr读数据整数时钟周期的同步电路及同步方法
IL297427A (en) 2020-04-20 2022-12-01 Proteantecs Ltd Inter-chip connectivity monitoring
US11815551B1 (en) 2022-06-07 2023-11-14 Proteantecs Ltd. Die-to-die connectivity monitoring using a clocked receiver
US12013800B1 (en) 2023-02-08 2024-06-18 Proteantecs Ltd. Die-to-die and chip-to-chip connectivity monitoring

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5269031A (en) * 1990-11-13 1993-12-14 Alexander James H Drive unit and clutch assembly for an adjustable bed
TW198135B (de) 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd
US5467464A (en) * 1993-03-09 1995-11-14 Apple Computer, Inc. Adaptive clock skew and duty cycle compensation for a serial data bus
JPH07154381A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd データ転送装置
JP2580999B2 (ja) 1994-04-12 1997-02-12 日本電気株式会社 Ｄｍａコントローラ
US6192482B1 (en) * 1994-06-17 2001-02-20 International Business Machines Corporation Self-timed parallel data bus interface to direct storage devices
US6112284A (en) * 1994-12-30 2000-08-29 Intel Corporation Method and apparatus for latching data from a memory resource at a datapath unit
JP2658958B2 (ja) 1995-03-31 1997-09-30 日本電気株式会社 Ｄｍａコントローラ
US5793687A (en) * 1996-12-03 1998-08-11 Mitsubishi Semiconductor America, Inc. Micro ROM testing system using micro ROM timing circuitry for testing operations
US5926838A (en) * 1997-03-19 1999-07-20 Micron Electronics Interface for high speed memory
US5948083A (en) * 1997-09-30 1999-09-07 S3 Incorporated System and method for self-adjusting data strobe
US6046477A (en) * 1998-03-17 2000-04-04 Micron Technology, Inc. Dense SOI programmable logic array structure
US6215145B1 (en) * 1998-04-06 2001-04-10 Micron Technology, Inc. Dense SOI flash memory array structure
US6225165B1 (en) * 1998-05-13 2001-05-01 Micron Technology, Inc. High density SRAM cell with latched vertical transistors
US6069506A (en) * 1998-05-20 2000-05-30 Micron Technology, Inc. Method and apparatus for improving the performance of digital delay locked loop circuits
US6141286A (en) * 1998-08-21 2000-10-31 Micron Technology, Inc. Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
US6408265B1 (en) * 1999-01-20 2002-06-18 Lsi Logic Corporation Metastability risk simulation analysis tool and method
US6654897B1 (en) * 1999-03-05 2003-11-25 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US6262611B1 (en) * 1999-06-24 2001-07-17 Nec Corporation High-speed data receiving circuit and method
JP2001035195A (ja) * 1999-07-19 2001-02-09 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JP2002082830A (ja) * 2000-02-14 2002-03-22 Mitsubishi Electric Corp インターフェイス回路
US6240003B1 (en) * 2000-05-01 2001-05-29 Micron Technology, Inc. DRAM content addressable memory using part of the content as an address
US6691214B1 (en) * 2000-08-29 2004-02-10 Micron Technology, Inc. DDR II write data capture calibration
US6889334B1 (en) * 2001-10-02 2005-05-03 Advanced Micro Devices, Inc. Multimode system for calibrating a data strobe delay for a memory read operation
US20030120989A1 (en) * 2001-12-26 2003-06-26 Zumkehr John F. Method and circuit to implement double data rate testing
US7076678B2 (en) * 2002-02-11 2006-07-11 Micron Technology, Inc. Method and apparatus for data transfer

Also Published As

Publication number Publication date
EP1479006A1 (de) 2004-11-24
ATE530985T1 (de) 2011-11-15
EP1679607A2 (de) 2006-07-12
US7818601B2 (en) 2010-10-19
EP1679607A3 (de) 2006-10-18
EP1677204A2 (de) 2006-07-05
ATE326035T1 (de) 2006-06-15
CN1630856A (zh) 2005-06-22
KR20040089613A (ko) 2004-10-21
EP1679607B1 (de) 2011-10-26
US20060129865A1 (en) 2006-06-15
KR100733951B1 (ko) 2007-06-29
AU2003205371A1 (en) 2003-09-04
US20080155141A1 (en) 2008-06-26
EP1677204B1 (de) 2010-11-17
DE60305162D1 (de) 2006-06-14
US7076678B2 (en) 2006-07-11
TWI257549B (en) 2006-07-01
DE60305162T2 (de) 2007-05-10
JP3987038B2 (ja) 2007-10-03
EP1677204A3 (de) 2006-10-18
TW200302969A (en) 2003-08-16
WO2003069486A1 (en) 2003-08-21
EP1479006B1 (de) 2006-05-10
CN100350402C (zh) 2007-11-21
US7356723B2 (en) 2008-04-08
US20030154416A1 (en) 2003-08-14
ATE488804T1 (de) 2010-12-15
JP2005525623A (ja) 2005-08-25

Similar Documents

Publication Publication Date Title
ATE488804T1 (de) Adaptives zeitsystem zur steuerung des speicherzugriffs
KR100883007B1 (ko) 데이지-체인 메모리 구조에서의 메모리 명령 지연 조절 방법
DE60223470D1 (de) Knotensteuerung für ein Datenspeicherungssystem
EP0327463A3 (de) Zur internen Erzeugung eines Schreibsignals fähige Halbleiterspeicheranordnung
KR100647747B1 (ko) 스트로브 신호를 지연하기 위한 시스템 및 방법
TWI256542B (en) Data latch time control method and device
KR19990023078A (ko) 클럭 시프트 회로 및 이것을 이용한 동기형 반도체 기억 장치
CN107077439A (zh) 存储器控制装置中输出延迟的动态选择
JP2007242236A (ja) 半導体メモリ装置及びその動作方法
DE69817298D1 (de) Vorrichtung zur Kommunikation zwischen Informationsverarbeitungseinheiten und mit einem gemeinsamen Bus verbundenenen Prozessoren
US7746724B2 (en) Asynchronous data transmission
KR100674994B1 (ko) 메모리 장치의 입력 버퍼와 메모리 제어장치 및 이를이용한 메모리 시스템
US7782699B2 (en) Auto-refresh controlling apparatus
TW200604802A (en) Associative memory support for data processing cross reference to related applications
WO2005088889A1 (en) Circuit comprising mutually asynchronous circuit modules
KR100821580B1 (ko) 반도체 메모리 장치
CA2220612A1 (en) Method and apparatus for inter-node deadlock avoidance on a parallel processing system
TW200511084A (en) Computer system using BIOS memory to store data of transmission controller
JP2002197860A (ja) 半導体集積回路と信号取り込み方法
JP2009042973A (ja) 通信制御システム
JP2002197056A (ja) ネットワーク用チップのインタフェース回路及びアクセスタイミング調整方法
ATE459049T1 (de) Speicherzugriff aus verschiedenen taktbereichen
JPH03257647A (ja) データ転送装置
JPH04168511A (ja) 半導体集積回路
JP2006180483A (ja) 半導体集積回路