DE60333712D1 - Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer - Google Patents

Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer

Info

Publication number
DE60333712D1
DE60333712D1 DE60333712T DE60333712T DE60333712D1 DE 60333712 D1 DE60333712 D1 DE 60333712D1 DE 60333712 T DE60333712 T DE 60333712T DE 60333712 T DE60333712 T DE 60333712T DE 60333712 D1 DE60333712 D1 DE 60333712D1
Authority
DE
Germany
Prior art keywords
donor wafer
image
thin layer
substrate
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60333712T
Other languages
German (de)
English (en)
Inventor
Fabrice Letertre
Yves Mathieu Levaillant
Eric Jalaguier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE60333712D1 publication Critical patent/DE60333712D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/174—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being Group III-V material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE60333712T 2002-10-07 2003-10-07 Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer Expired - Lifetime DE60333712D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0212405A FR2845523B1 (fr) 2002-10-07 2002-10-07 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee

Publications (1)

Publication Number Publication Date
DE60333712D1 true DE60333712D1 (de) 2010-09-23

Family

ID=32011448

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60333712T Expired - Lifetime DE60333712D1 (de) 2002-10-07 2003-10-07 Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer

Country Status (6)

Country Link
US (3) US7008859B2 (https=)
EP (1) EP1408545B1 (https=)
JP (1) JP4854921B2 (https=)
AT (1) ATE477589T1 (https=)
DE (1) DE60333712D1 (https=)
FR (1) FR2845523B1 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
FR2856192B1 (fr) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator Procede de realisation de structure heterogene et structure obtenue par un tel procede
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
EP1571705A3 (fr) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Réalisation d'une entité en matériau semiconducteur sur substrat
WO2006082467A1 (en) * 2005-02-01 2006-08-10 S.O.I.Tec Silicon On Insulator Technologies Substrate for crystal growing a nitride semiconductor
US7244630B2 (en) * 2005-04-05 2007-07-17 Philips Lumileds Lighting Company, Llc A1InGaP LED having reduced temperature dependence
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
CN1992173B (zh) * 2005-11-30 2010-04-21 硅起源股份有限公司 用于注入键合衬底以便导电的方法和结构
WO2008096194A1 (en) * 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
US20090092159A1 (en) * 2007-05-28 2009-04-09 Sumitomo Electric Industries, Ltd. Semiconductor light-emitting device with tunable emission wavelength
US20090174018A1 (en) * 2008-01-09 2009-07-09 Micron Technology, Inc. Construction methods for backside illuminated image sensors
FR2926674B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
CN101904017A (zh) * 2008-02-26 2010-12-01 硅绝缘体技术有限公司 制造半导体衬底的方法
US20100044827A1 (en) * 2008-08-22 2010-02-25 Kinik Company Method for making a substrate structure comprising a film and substrate structure made by same method
EP2202795A1 (en) * 2008-12-24 2010-06-30 S.O.I. TEC Silicon Method for fabricating a semiconductor substrate and semiconductor substrate
FR2953328B1 (fr) * 2009-12-01 2012-03-30 S O I Tec Silicon On Insulator Tech Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques
US8748288B2 (en) 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
EP2654075B1 (de) 2010-03-31 2016-09-28 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
DE112012003260T5 (de) 2011-08-05 2014-05-15 Sumitomo Electric Industries, Ltd. Substrat, Halbleitervorrichtung und Verfahren zur Herstellung derselben
FR2982071B1 (fr) * 2011-10-27 2014-05-16 Commissariat Energie Atomique Procede de lissage d'une surface par traitement thermique
FR2994766B1 (fr) * 2012-08-23 2014-09-05 Commissariat Energie Atomique Procede de transfert d'un film d'inp
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
CN105374664A (zh) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 一种InP薄膜复合衬底的制备方法
FR3045678B1 (fr) * 2015-12-22 2017-12-22 Soitec Silicon On Insulator Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
FR3045677B1 (fr) 2015-12-22 2019-07-19 Soitec Procede de fabrication d'une couche monocristalline, notamment piezoelectrique
US10985204B2 (en) * 2016-02-16 2021-04-20 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces
FR3091000B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Procede de fabrication d’un substrat pour un capteur d’image de type face avant
CN113223928B (zh) * 2021-04-16 2024-01-12 西安电子科技大学 一种基于转移键合的氧化镓外延生长方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2596777B1 (fr) * 1986-04-08 1994-01-21 Etat Francais Cnet Procede de preparation de semi-isolants 3-5 mono-cristallins par dopage et application des semi-isolants ainsi obtenus
US4738934A (en) * 1986-05-16 1988-04-19 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making indium phosphide devices
IL100979A0 (en) 1991-03-18 1992-11-15 Hughes Aircraft Co Method for establishing an electrical field at a surface of a semiconductor device
JP2932787B2 (ja) * 1991-10-03 1999-08-09 日立電線株式会社 化合物半導体ウェハの製造方法
US5227313A (en) * 1992-07-24 1993-07-13 Eastman Kodak Company Process for making backside illuminated image sensors
US5244817A (en) * 1992-08-03 1993-09-14 Eastman Kodak Company Method of making backside illuminated image sensors
US5270221A (en) * 1992-11-05 1993-12-14 Hughes Aircraft Company Method of fabricating high quantum efficiency solid state sensors
JPH08139297A (ja) * 1994-09-14 1996-05-31 Nippon Telegr & Teleph Corp <Ntt> Ｓｏｉ基板の製造方法
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
JP4304884B2 (ja) * 2001-06-06 2009-07-29 日本電気株式会社 半導体装置及びその製造方法
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
US7169226B2 (en) * 2003-07-01 2007-01-30 International Business Machines Corporation Defect reduction by oxidation of silicon

Also Published As

Publication number Publication date
JP2004179630A (ja) 2004-06-24
ATE477589T1 (de) 2010-08-15
US20040121558A1 (en) 2004-06-24
FR2845523A1 (fr) 2004-04-09
EP1408545A2 (en) 2004-04-14
US20080248631A1 (en) 2008-10-09
FR2845523B1 (fr) 2005-10-28
US7645684B2 (en) 2010-01-12
EP1408545B1 (en) 2010-08-11
JP4854921B2 (ja) 2012-01-18
US20060060922A1 (en) 2006-03-23
EP1408545A3 (en) 2004-08-04
US7535115B2 (en) 2009-05-19
US7008859B2 (en) 2006-03-07

Similar Documents

Publication Publication Date Title
DE60333712D1 (de) Verfahren zur Herstellung eines Substrats durch den Transfer eines Geber-Wafers mit Fremdatomen, und ein entsprechender Geber-Wafer
JP2004179630A5 (https=)
ATE427559T1 (de) Verfahren zur herstellung eines substrats, insbesondere fur optische, elektronische oder optoelektronische anwendungen, und mittels dieses verfahrens erhaltenes substrat
ATE473518T1 (de) Verfahren zur herstellung von dünnschichtbauelementen für solarzellen oder soi- anwendungen
ATE373121T1 (de) Verfahren zur herstellung einer epitaktischen schicht
ATE465514T1 (de) Herstellungsverfahren für eine bruchzone in einem substrat durch koimplantation
ATE534759T1 (de) Verfahren zur herstellung eines freistehenden substrates aus monokristallinem halbleitermaterial
ATE531077T1 (de) Belastungsfreies zusammengesetztes substrat und verfahren zur herstellung eines solchen zusammengesetzten substrats
KR960030316A (ko) Soi 기판의 제조방법
DE69728022D1 (de) Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht
WO2002043124A3 (fr) Procede de fabrication d&#39;un substrat contenant une couche mince sur un support et substrat obtenu par ce procede
WO2007110515A3 (fr) Procede de detachement d&#39;un film mince par fusion de precipites
TW200715380A (en) Process for lateral disjonting of a semiconductor wafer and opto-electronic element
TW200520087A (en) Process for obtaining a thin layer of increased quality by co-implantation and thermal annealing
TWI267186B (en) Process for preparation of separable semiconductor assemblies, particularly to form substrates for electronics, optoelectronics and optics
DE59608710D1 (de) Dotierverfahren zur herstellung von homoübergängen in halbleitersubstraten
FR2845518B1 (fr) Realisation d&#39;un substrat semiconducteur demontable et obtention d&#39;un element semiconducteur
ATE490549T1 (de) Herstellung von gitterabstimmungs- halbleitersubstraten
TW200721373A (en) Method for recycling an epitaxied donor wafer
TW200507076A (en) Method for manufacturing semiconductor device
ATE505816T1 (de) Verfahren zur herstellung eines indium-gallium- aluminium-nitrid-dünnfilms auf einem siliziumsubstrat
ATE370264T1 (de) Verfahren zur herstellung von substraten, insbesondere für die optik, elektronik und optoelektronik
ATE332211T1 (de) Verbindungssystem zum befestigen von halbleiterplatten sowie verfahren zur herstellung von halbleiterplatten
ATE438196T1 (de) Verfahren zur herstellung einer relaxierten sige- schicht
US7871900B2 (en) Quality of a thin layer through high-temperature thermal annealing

Legal Events

Date Code Title Description
R082 Change of representative

Ref document number: 1408545

Country of ref document: EP

Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE

R081 Change of applicant/patentee

Ref document number: 1408545

Country of ref document: EP

Owner name: SOITEC, FR

Free format text: FORMER OWNER: COMMISSARIAT A L'ENERGIE ATOMIQ, S.O.I.TEC SILICON ON INSULATOR, , FR

Effective date: 20120905

Ref document number: 1408545

Country of ref document: EP

Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA), FR

Free format text: FORMER OWNER: COMMISSARIAT A L'ENERGIE ATOMIQ, S.O.I.TEC SILICON ON INSULATOR, , FR

Effective date: 20120905

R082 Change of representative

Ref document number: 1408545

Country of ref document: EP

Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE

Effective date: 20120905