DE602005007003D1 - Verfahren zur erkennung von resistiv-offen-defekten in halbleiterspeichern - Google Patents
Verfahren zur erkennung von resistiv-offen-defekten in halbleiterspeichernInfo
- Publication number
- DE602005007003D1 DE602005007003D1 DE602005007003T DE602005007003T DE602005007003D1 DE 602005007003 D1 DE602005007003 D1 DE 602005007003D1 DE 602005007003 T DE602005007003 T DE 602005007003T DE 602005007003 T DE602005007003 T DE 602005007003T DE 602005007003 D1 DE602005007003 D1 DE 602005007003D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- bits
- data bits
- address
- open defects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US55670604P | 2004-03-26 | 2004-03-26 | |
PCT/IB2005/051006 WO2005093761A1 (en) | 2004-03-26 | 2005-03-23 | Method for detecting resistive-open defects in semiconductor memories |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005007003D1 true DE602005007003D1 (de) | 2008-07-03 |
Family
ID=34962300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005007003T Active DE602005007003D1 (de) | 2004-03-26 | 2005-03-23 | Verfahren zur erkennung von resistiv-offen-defekten in halbleiterspeichern |
Country Status (7)
Country | Link |
---|---|
US (1) | US7536610B2 (de) |
EP (1) | EP1738375B1 (de) |
JP (1) | JP2007531191A (de) |
CN (1) | CN1934655B (de) |
AT (1) | ATE396484T1 (de) |
DE (1) | DE602005007003D1 (de) |
WO (1) | WO2005093761A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100582391B1 (ko) * | 2004-04-08 | 2006-05-22 | 주식회사 하이닉스반도체 | 반도체 소자에서의 지연 요소의 지연 검출 장치 및 방법 |
US7475314B2 (en) * | 2005-12-15 | 2009-01-06 | Intel Corporation | Mechanism for read-only memory built-in self-test |
CN102486938B (zh) * | 2010-12-06 | 2015-01-07 | 北大方正集团有限公司 | 一种快速检测存储器的方法及装置 |
WO2013100956A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Memory timing optimization using pattern based signaling modulation |
US9076558B2 (en) * | 2012-11-01 | 2015-07-07 | Nanya Technology Corporation | Memory test system and memory test method |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399912A (en) * | 1992-01-13 | 1995-03-21 | Hitachi, Ltd. | Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error |
JPH09507945A (ja) * | 1994-11-09 | 1997-08-12 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | メモリアドレスデコーダと誤り許容メモリアドレスデコーダをテストする方法 |
US5621739A (en) * | 1996-05-07 | 1997-04-15 | Intel Corporation | Method and apparatus for buffer self-test and characterization |
US5787092A (en) * | 1997-05-27 | 1998-07-28 | Hewlett-Packard Co. | Test chip circuit for on-chip timing characterization |
KR100211609B1 (ko) * | 1997-06-30 | 1999-08-02 | 윤종용 | 이중에지 클록을 사용한 집적회로 소자 검사방법 |
US5936977A (en) * | 1997-09-17 | 1999-08-10 | Cypress Semiconductor Corp. | Scan path circuitry including a programmable delay circuit |
TW535161B (en) * | 1999-12-03 | 2003-06-01 | Nec Electronics Corp | Semiconductor memory device and its testing method |
DE10035169A1 (de) * | 2000-07-19 | 2002-02-07 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Testen von Setup-Zeit und Hold-Zeit von Signalen einer Schaltung mit getakteter Datenübertragung |
US6829728B2 (en) * | 2000-11-13 | 2004-12-07 | Wu-Tung Cheng | Full-speed BIST controller for testing embedded synchronous memories |
DE602004020887D1 (de) * | 2003-05-22 | 2009-06-10 | Nxp Bv | Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen |
-
2004
- 2004-07-15 US US10/892,696 patent/US7536610B2/en not_active Expired - Fee Related
-
2005
- 2005-03-23 EP EP05709081A patent/EP1738375B1/de not_active Not-in-force
- 2005-03-23 CN CN2005800095975A patent/CN1934655B/zh not_active Expired - Fee Related
- 2005-03-23 DE DE602005007003T patent/DE602005007003D1/de active Active
- 2005-03-23 AT AT05709081T patent/ATE396484T1/de not_active IP Right Cessation
- 2005-03-23 WO PCT/IB2005/051006 patent/WO2005093761A1/en active IP Right Grant
- 2005-03-23 JP JP2007504555A patent/JP2007531191A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO2005093761A1 (en) | 2005-10-06 |
EP1738375B1 (de) | 2008-05-21 |
US20050216799A1 (en) | 2005-09-29 |
ATE396484T1 (de) | 2008-06-15 |
EP1738375A1 (de) | 2007-01-03 |
CN1934655B (zh) | 2011-06-08 |
JP2007531191A (ja) | 2007-11-01 |
US7536610B2 (en) | 2009-05-19 |
CN1934655A (zh) | 2007-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2002039460A3 (en) | Full-speed bist controller for testing embedded synchronous memories | |
JP2009289374A5 (de) | ||
US20070266278A1 (en) | Method for at-speed testing of memory interface using scan | |
ATE408152T1 (de) | Prüfung von schaltungen mit mehreren taktdomänen | |
ATE396484T1 (de) | Verfahren zur erkennung von resistiv-offen- defekten in halbleiterspeichern | |
TW200627923A (en) | Testing apparatus and testing method | |
WO2007103745A3 (en) | At-speed multi-port memory array test method and apparatus | |
DE602006014549D1 (de) | Verfahren und system für debug und test unter verwendung replizierter logik | |
TWI479499B (zh) | 測試裝置以及測試方法 | |
TW200739109A (en) | Test method, test system and assist board | |
Putman et al. | Enhanced timing-based transition delay testing for small delay defects | |
US7783943B2 (en) | Method and apparatus for testing a random access memory device | |
ATE491208T1 (de) | Verfahren und vorrichtung zur verbesserung der speicherleistungsfähigkeit | |
US20110270599A1 (en) | Method for testing integrated circuit and semiconductor memory device | |
US20100090718A1 (en) | Semiconductor device, and development supporting device | |
DE60103635D1 (de) | Vorrichtung und verfahren zur verbesserung der prüfung, des ertrags und der leistung von vlsi schaltungen | |
ATE511694T1 (de) | Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern | |
JP4511882B2 (ja) | 試験装置及び試験方法 | |
KR100885051B1 (ko) | 반도체 메모리 테스트 장치 및 반도체 메모리 테스트 방법 | |
TW200508637A (en) | Circuit testing arrangement and approach therefor | |
JP5625241B2 (ja) | 半導体装置及びその試験方法 | |
TW201510721A (zh) | 時序分析方法以及機器可讀媒體 | |
JP2006134374A (ja) | 半導体装置及び半導体装置のテスト方法 | |
JP2002343097A (ja) | Ramテスト回路 | |
JP2006079678A (ja) | メモリテスト回路およびメモリテスト方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |