DE60103635D1 - Vorrichtung und verfahren zur verbesserung der prüfung, des ertrags und der leistung von vlsi schaltungen - Google Patents
Vorrichtung und verfahren zur verbesserung der prüfung, des ertrags und der leistung von vlsi schaltungenInfo
- Publication number
- DE60103635D1 DE60103635D1 DE60103635T DE60103635T DE60103635D1 DE 60103635 D1 DE60103635 D1 DE 60103635D1 DE 60103635 T DE60103635 T DE 60103635T DE 60103635 T DE60103635 T DE 60103635T DE 60103635 D1 DE60103635 D1 DE 60103635D1
- Authority
- DE
- Germany
- Prior art keywords
- improving
- vlsi
- test
- performance
- yield
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/533,226 US6320803B1 (en) | 2000-03-23 | 2000-03-23 | Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits |
US533226 | 2000-03-23 | ||
PCT/US2001/008530 WO2001071726A2 (en) | 2000-03-23 | 2001-03-15 | Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60103635D1 true DE60103635D1 (de) | 2004-07-08 |
DE60103635T2 DE60103635T2 (de) | 2005-06-09 |
Family
ID=24125037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60103635T Expired - Fee Related DE60103635T2 (de) | 2000-03-23 | 2001-03-15 | Vorrichtung und verfahren zur verbesserung der prüfung, des ertrags und der leistung von vlsi schaltungen |
Country Status (6)
Country | Link |
---|---|
US (1) | US6320803B1 (de) |
EP (1) | EP1273010B1 (de) |
KR (1) | KR100743292B1 (de) |
DE (1) | DE60103635T2 (de) |
TW (1) | TW511091B (de) |
WO (1) | WO2001071726A2 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW556204B (en) * | 2001-04-27 | 2003-10-01 | Infineon Technologies Ag | Method for test-by-test writing to the cell array of a semiconductor memory |
US6731127B2 (en) * | 2001-12-21 | 2004-05-04 | Texas Instruments Incorporated | Parallel integrated circuit test apparatus and test method |
US6897670B2 (en) | 2001-12-21 | 2005-05-24 | Texas Instruments Incorporated | Parallel integrated circuit test apparatus and test method |
KR100472004B1 (ko) * | 2002-07-30 | 2005-03-10 | 동부아남반도체 주식회사 | 반도체 장치 |
KR100699827B1 (ko) * | 2004-03-23 | 2007-03-27 | 삼성전자주식회사 | 메모리 모듈 |
US7830737B2 (en) | 2008-06-27 | 2010-11-09 | International Business Machines Corporation | SMI memory read data capture margin characterization circuits and methods |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60210000A (ja) * | 1984-04-04 | 1985-10-22 | Hitachi Ltd | フエイルメモリ |
JP3251637B2 (ja) * | 1992-05-06 | 2002-01-28 | 株式会社東芝 | 半導体記憶装置 |
JP3240709B2 (ja) * | 1992-10-30 | 2001-12-25 | 株式会社アドバンテスト | メモリ試験装置 |
US5671392A (en) * | 1995-04-11 | 1997-09-23 | United Memories, Inc. | Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array |
US5996106A (en) * | 1997-02-04 | 1999-11-30 | Micron Technology, Inc. | Multi bank test mode for memory devices |
EP0884735B1 (de) * | 1997-05-30 | 2004-03-17 | Fujitsu Limited | Halbleiterspeicherschaltung mit einem Selektor für mehrere Wortleitungen, und Prüfverfahren dafür |
JPH1166841A (ja) * | 1997-08-22 | 1999-03-09 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5959929A (en) * | 1997-12-29 | 1999-09-28 | Micron Technology, Inc. | Method for writing to multiple banks of a memory device |
-
2000
- 2000-03-23 US US09/533,226 patent/US6320803B1/en not_active Expired - Fee Related
-
2001
- 2001-03-15 DE DE60103635T patent/DE60103635T2/de not_active Expired - Fee Related
- 2001-03-15 WO PCT/US2001/008530 patent/WO2001071726A2/en active IP Right Grant
- 2001-03-15 KR KR1020027012546A patent/KR100743292B1/ko not_active IP Right Cessation
- 2001-03-15 EP EP01922434A patent/EP1273010B1/de not_active Expired - Lifetime
- 2001-03-23 TW TW090106958A patent/TW511091B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20030016240A (ko) | 2003-02-26 |
TW511091B (en) | 2002-11-21 |
WO2001071726A2 (en) | 2001-09-27 |
EP1273010B1 (de) | 2004-06-02 |
KR100743292B1 (ko) | 2007-07-26 |
WO2001071726A3 (en) | 2002-05-23 |
EP1273010A2 (de) | 2003-01-08 |
DE60103635T2 (de) | 2005-06-09 |
US6320803B1 (en) | 2001-11-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
8339 | Ceased/non-payment of the annual fee |