DE60110199D1 - Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler - Google Patents

Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler

Info

Publication number
DE60110199D1
DE60110199D1 DE60110199T DE60110199T DE60110199D1 DE 60110199 D1 DE60110199 D1 DE 60110199D1 DE 60110199 T DE60110199 T DE 60110199T DE 60110199 T DE60110199 T DE 60110199T DE 60110199 D1 DE60110199 D1 DE 60110199D1
Authority
DE
Germany
Prior art keywords
scan test
tap
debugging
internal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60110199T
Other languages
English (en)
Other versions
DE60110199T2 (de
Inventor
Kenneth Jaramillo
Varaprasda Vajjhala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE60110199D1 publication Critical patent/DE60110199D1/de
Publication of DE60110199T2 publication Critical patent/DE60110199T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measuring Leads Or Probes (AREA)
DE60110199T 2000-10-02 2001-10-02 Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler Expired - Lifetime DE60110199T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US678412 2000-10-02
US09/678,412 US6785854B1 (en) 2000-10-02 2000-10-02 Test access port (TAP) controller system and method to debug internal intermediate scan test faults
PCT/EP2001/011401 WO2002029568A2 (en) 2000-10-02 2001-10-02 A test access port (tap) controller system and method to debug internal intermediate scan test faults

Publications (2)

Publication Number Publication Date
DE60110199D1 true DE60110199D1 (de) 2005-05-25
DE60110199T2 DE60110199T2 (de) 2006-01-19

Family

ID=24722674

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60110199T Expired - Lifetime DE60110199T2 (de) 2000-10-02 2001-10-02 Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler

Country Status (6)

Country Link
US (1) US6785854B1 (de)
EP (1) EP1236053B1 (de)
JP (1) JP3996055B2 (de)
AT (1) ATE293797T1 (de)
DE (1) DE60110199T2 (de)
WO (1) WO2002029568A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7200783B2 (en) * 2003-11-04 2007-04-03 Texas Instruments Incorporated Removable and replaceable TAP domain selection circuitry
US7072818B1 (en) 1999-11-30 2006-07-04 Synplicity, Inc. Method and system for debugging an electronic system
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
US7222315B2 (en) 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US7039840B2 (en) * 2002-05-20 2006-05-02 Mindspeed Technologies, Inc. Method and apparatus for high update rate integrated circuit boundary scan
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
JP2006519388A (ja) * 2003-03-04 2006-08-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ テスト信号の自動検出及び経路指定
DE60323851D1 (de) * 2003-12-17 2008-11-13 St Microelectronics Res & Dev TAP Multiplexer
US7475303B1 (en) * 2003-12-29 2009-01-06 Mips Technologies, Inc. HyperJTAG system including debug probe, on-chip instrumentation, and protocol
US7243318B1 (en) * 2004-08-30 2007-07-10 Sprint Communications Company L.P. Integrated test processor (ITP) for a system on chip (SOC) that includes a network on chip (NOC)
US8437281B2 (en) * 2007-03-27 2013-05-07 Cisco Technology, Inc. Distributed real-time data mixing for conferencing
EP2133705A4 (de) * 2007-03-29 2011-03-30 Fujitsu Ltd Fehlerlokalisierungseinrichtung, fehlerlokalisierungsverfahren und integrierte schaltung
EP2223948B1 (de) * 2007-11-01 2013-01-23 Adeka Corporation Salzverbindung, initiator für die kationische polymerisation und kationisch polymerisierbare zusammensetzung
US9121892B2 (en) 2012-08-13 2015-09-01 Analog Devices Global Semiconductor circuit and methodology for in-system scan testing
DE112019007376T5 (de) 2019-05-31 2022-02-17 Micron Technology, Inc. Speicherkomponente mit einer jtag-testschnittstelle mit einer matrix von befehlsregistern

Family Cites Families (19)

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ZA834008B (en) * 1982-06-11 1984-03-28 Int Computers Ltd Data processing system
JPH01217278A (ja) * 1988-02-26 1989-08-30 Mitsubishi Electric Corp 集積回路
JPH01263739A (ja) * 1988-04-14 1989-10-20 Nec Corp 情報処理装置
US5048021A (en) * 1989-08-28 1991-09-10 At&T Bell Laboratories Method and apparatus for generating control signals
JP2627464B2 (ja) * 1990-03-29 1997-07-09 三菱電機株式会社 集積回路装置
JPH04250371A (ja) * 1991-01-28 1992-09-07 Toshiba Corp テスト回路
US5254942A (en) * 1991-04-25 1993-10-19 Daniel D'Souza Single chip IC tester architecture
JPH0763821A (ja) * 1993-06-30 1995-03-10 Kawasaki Steel Corp テスト回路
TW253942B (de) * 1994-01-31 1995-08-11 At & T Corp
JP3310096B2 (ja) * 1994-03-30 2002-07-29 株式会社東芝 集積回路装置
GB2290877B (en) * 1994-07-01 1997-08-20 Advanced Risc Mach Ltd Integrated circuit test controller
US5636227A (en) 1994-07-08 1997-06-03 Advanced Risc Machines Limited Integrated circuit test mechansim and method
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US5862152A (en) * 1995-11-13 1999-01-19 Motorola, Inc. Hierarchically managed boundary-scan testable module and method
US5898701A (en) 1995-12-21 1999-04-27 Cypress Semiconductor Corporation Method and apparatus for testing a device
US5774475A (en) 1996-12-05 1998-06-30 National Semiconductor Corporation Testing scheme that re-uses original stimulus for testing circuitry embedded within a larger circuit
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
US6314539B1 (en) * 1998-10-21 2001-11-06 Xilinx, Inc. Boundary-scan register cell with bypass circuit
US6584590B1 (en) * 1999-08-13 2003-06-24 Lucent Technologies Inc. JTAG port-sharing device

Also Published As

Publication number Publication date
JP3996055B2 (ja) 2007-10-24
DE60110199T2 (de) 2006-01-19
WO2002029568A3 (en) 2002-06-13
ATE293797T1 (de) 2005-05-15
EP1236053A2 (de) 2002-09-04
WO2002029568A2 (en) 2002-04-11
JP2004510989A (ja) 2004-04-08
US6785854B1 (en) 2004-08-31
EP1236053B1 (de) 2005-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL