ATE472106T1 - Ic-testverfahren und vorrichtung - Google Patents
Ic-testverfahren und vorrichtungInfo
- Publication number
- ATE472106T1 ATE472106T1 AT06809583T AT06809583T ATE472106T1 AT E472106 T1 ATE472106 T1 AT E472106T1 AT 06809583 T AT06809583 T AT 06809583T AT 06809583 T AT06809583 T AT 06809583T AT E472106 T1 ATE472106 T1 AT E472106T1
- Authority
- AT
- Austria
- Prior art keywords
- output
- shift register
- storage element
- parallel
- register storage
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05109894 | 2005-10-24 | ||
PCT/IB2006/053756 WO2007049173A1 (en) | 2005-10-24 | 2006-10-12 | Ic testing methods and apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE472106T1 true ATE472106T1 (de) | 2010-07-15 |
Family
ID=37831751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06809583T ATE472106T1 (de) | 2005-10-24 | 2006-10-12 | Ic-testverfahren und vorrichtung |
Country Status (8)
Country | Link |
---|---|
US (1) | US7941719B2 (de) |
EP (1) | EP1943533B1 (de) |
JP (1) | JP4966974B2 (de) |
CN (1) | CN101297207B (de) |
AT (1) | ATE472106T1 (de) |
DE (1) | DE602006015082D1 (de) |
TW (1) | TW200732682A (de) |
WO (1) | WO2007049173A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE602006012082D1 (de) | 2005-10-24 | 2010-03-18 | Nxp Bv | Ic-testverfahren und vorrichtung |
US8856601B2 (en) * | 2009-08-25 | 2014-10-07 | Texas Instruments Incorporated | Scan compression architecture with bypassable scan chains for low test mode power |
US8627159B2 (en) | 2010-11-11 | 2014-01-07 | Qualcomm Incorporated | Feedback scan isolation and scan bypass architecture |
CN102156259B (zh) * | 2011-04-02 | 2013-07-03 | 北京大学深圳研究生院 | 一种集成电路的测试方法及一种集成电路 |
US9551747B2 (en) * | 2014-12-12 | 2017-01-24 | International Business Machines Corporation | Inserting bypass structures at tap points to reduce latch dependency during scan testing |
US9588176B1 (en) * | 2015-01-30 | 2017-03-07 | Altera Corporation | Techniques for using scan storage circuits |
CN105203946B (zh) * | 2015-10-30 | 2018-05-18 | 中国科学院微电子研究所 | 一种嵌入式芯核测试壳装置及其设计方法 |
US9897653B2 (en) * | 2016-03-16 | 2018-02-20 | Stmicroelectronics (Grenoble 2) Sas | Scan chain circuit supporting logic self test pattern injection during run time |
US10310013B2 (en) * | 2016-12-12 | 2019-06-04 | Samsung Electronics Co., Ltd. | Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains |
EP3428665B1 (de) * | 2017-07-11 | 2020-03-25 | Nxp B.V. | Fehlererkennung in registern |
US11320485B1 (en) * | 2020-12-31 | 2022-05-03 | Nxp Usa, Inc. | Scan wrapper architecture for system-on-chip |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62242873A (ja) | 1986-04-14 | 1987-10-23 | Nec Corp | 集積回路 |
US6304987B1 (en) * | 1995-06-07 | 2001-10-16 | Texas Instruments Incorporated | Integrated test circuit |
JP3983318B2 (ja) * | 1995-05-31 | 2007-09-26 | テキサス インスツルメンツ インコーポレイテツド | 低オーバヘッド入力および出力境界走査セルを含む集積回路 |
US6560734B1 (en) * | 1998-06-19 | 2003-05-06 | Texas Instruments Incorporated | IC with addressable test port |
JP2001153928A (ja) | 1999-11-26 | 2001-06-08 | Nec Corp | バウンダリスキャン回路 |
US6877122B2 (en) * | 2001-12-21 | 2005-04-05 | Texas Instruments Incorporated | Link instruction register providing test control signals to core wrappers |
US6925583B1 (en) * | 2002-01-09 | 2005-08-02 | Xilinx, Inc. | Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device |
KR100505662B1 (ko) * | 2002-12-30 | 2005-08-03 | 삼성전자주식회사 | 칩 사이즈를 감소시키는 스캔 테스트 회로를 구비한반도체 장치, 및 그 테스트 방법 |
JP4274806B2 (ja) * | 2003-01-28 | 2009-06-10 | 株式会社リコー | 半導体集積回路およびスキャンテスト法 |
EP1595156B1 (de) | 2003-02-10 | 2006-11-29 | Koninklijke Philips Electronics N.V. | Testen von integrierten schaltungen |
ATE403160T1 (de) * | 2004-01-19 | 2008-08-15 | Nxp Bv | Testarchitektur und -verfahren |
JP2007524947A (ja) * | 2004-02-17 | 2007-08-30 | アンスティテュ ナシオナル ポリテクニーク ド グレノーブル | 集積回路のipコアのテスト手段のリモート制御を行うことができる通信手段を備える集積回路チップ |
TWI263058B (en) * | 2004-12-29 | 2006-10-01 | Ind Tech Res Inst | Wrapper testing circuits and method thereof for system-on-a-chip |
DE602006012082D1 (de) | 2005-10-24 | 2010-03-18 | Nxp Bv | Ic-testverfahren und vorrichtung |
DE602006013339D1 (de) | 2005-10-24 | 2010-05-12 | Nxp Bv | Ic-testverfahren und vorrichtung |
-
2006
- 2006-10-12 DE DE602006015082T patent/DE602006015082D1/de active Active
- 2006-10-12 US US12/090,971 patent/US7941719B2/en not_active Expired - Fee Related
- 2006-10-12 WO PCT/IB2006/053756 patent/WO2007049173A1/en active Application Filing
- 2006-10-12 EP EP06809583A patent/EP1943533B1/de not_active Not-in-force
- 2006-10-12 AT AT06809583T patent/ATE472106T1/de not_active IP Right Cessation
- 2006-10-12 CN CN2006800393729A patent/CN101297207B/zh not_active Expired - Fee Related
- 2006-10-12 JP JP2008537249A patent/JP4966974B2/ja not_active Expired - Fee Related
- 2006-10-20 TW TW095138810A patent/TW200732682A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
WO2007049173A1 (en) | 2007-05-03 |
US20080255780A1 (en) | 2008-10-16 |
DE602006015082D1 (de) | 2010-08-05 |
JP4966974B2 (ja) | 2012-07-04 |
EP1943533B1 (de) | 2010-06-23 |
JP2009512874A (ja) | 2009-03-26 |
CN101297207A (zh) | 2008-10-29 |
CN101297207B (zh) | 2012-03-28 |
US7941719B2 (en) | 2011-05-10 |
TW200732682A (en) | 2007-09-01 |
EP1943533A1 (de) | 2008-07-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |