ATE403160T1 - Testarchitektur und -verfahren - Google Patents

Testarchitektur und -verfahren

Info

Publication number
ATE403160T1
ATE403160T1 AT05702665T AT05702665T ATE403160T1 AT E403160 T1 ATE403160 T1 AT E403160T1 AT 05702665 T AT05702665 T AT 05702665T AT 05702665 T AT05702665 T AT 05702665T AT E403160 T1 ATE403160 T1 AT E403160T1
Authority
AT
Austria
Prior art keywords
test
enable signal
test access
modules
global enable
Prior art date
Application number
AT05702665T
Other languages
English (en)
Inventor
Erik J Marinissen
Thomas F Waayers
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE403160T1 publication Critical patent/ATE403160T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Communication Control (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT05702665T 2004-01-19 2005-01-13 Testarchitektur und -verfahren ATE403160T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04100141 2004-01-19

Publications (1)

Publication Number Publication Date
ATE403160T1 true ATE403160T1 (de) 2008-08-15

Family

ID=34802649

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05702665T ATE403160T1 (de) 2004-01-19 2005-01-13 Testarchitektur und -verfahren

Country Status (8)

Country Link
US (1) US7620866B2 (de)
EP (1) EP1709454B1 (de)
JP (1) JP2007524088A (de)
KR (1) KR101118407B1 (de)
CN (1) CN100541217C (de)
AT (1) ATE403160T1 (de)
DE (1) DE602005008552D1 (de)
WO (1) WO2005071425A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7657790B2 (en) * 2006-04-05 2010-02-02 Texas Instruments Incorporated Scan frame based test access mechanisms
WO2007049172A1 (en) * 2005-10-24 2007-05-03 Nxp B.V. Ic testing methods and apparatus
EP1943531B1 (de) * 2005-10-24 2010-03-31 Nxp B.V. Ic-testverfahren und vorrichtung
WO2007049173A1 (en) * 2005-10-24 2007-05-03 Nxp B.V. Ic testing methods and apparatus
WO2007069097A1 (en) * 2005-11-02 2007-06-21 Nxp B.V. Ic testing methods and apparatus
US7519884B2 (en) * 2006-06-16 2009-04-14 Texas Instruments Incorporated TAM controller for plural test access mechanisms
US7954022B2 (en) * 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
US8531197B2 (en) * 2008-07-17 2013-09-10 Freescale Semiconductor, Inc. Integrated circuit die, an integrated circuit package and a method for connecting an integrated circuit die to an external device
KR20100103212A (ko) 2009-03-13 2010-09-27 삼성전자주식회사 복수개의 테스트 모듈을 구비하는 테스트 보드 및 이를 구비하는 테스트 시스템
US20100332177A1 (en) * 2009-06-30 2010-12-30 National Tsing Hua University Test access control apparatus and method thereof
US8918689B2 (en) * 2010-07-19 2014-12-23 Stmicroelectronics International N.V. Circuit for testing integrated circuits
CN104081465B (zh) * 2011-12-28 2020-05-19 英特尔公司 用于存储器电路测试引擎的通用地址加扰器
US9190173B2 (en) 2012-03-30 2015-11-17 Intel Corporation Generic data scrambler for memory circuit test engine
US9568551B1 (en) * 2015-09-16 2017-02-14 Freescale Semiconductor, Inc. Scan wrapper circuit for integrated circuit
CN109857024B (zh) * 2019-02-01 2021-11-12 京微齐力(北京)科技有限公司 人工智能模块的单元性能测试方法和系统芯片

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860290A (en) * 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules
US6378090B1 (en) * 1998-04-24 2002-04-23 Texas Instruments Incorporated Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port
US6886110B2 (en) * 2000-11-21 2005-04-26 Wind River Systems, Inc. Multiple device scan chain emulation/debugging
US7103814B2 (en) * 2002-10-25 2006-09-05 International Business Machines Corporation Testing logic and embedded memory in parallel
KR100514319B1 (ko) * 2003-12-02 2005-09-13 조상욱 시스템 온 칩의 테스트를 위한 코아 접속 스위치
US7181663B2 (en) * 2004-03-01 2007-02-20 Verigy Pte, Ltd. Wireless no-touch testing of integrated circuits
US7231563B2 (en) * 2004-05-26 2007-06-12 Lsi Corporation Method and apparatus for high speed testing of latch based random access memory

Also Published As

Publication number Publication date
CN100541217C (zh) 2009-09-16
JP2007524088A (ja) 2007-08-23
US7620866B2 (en) 2009-11-17
DE602005008552D1 (de) 2008-09-11
EP1709454A1 (de) 2006-10-11
US20070208970A1 (en) 2007-09-06
CN1910463A (zh) 2007-02-07
KR20070029654A (ko) 2007-03-14
WO2005071425A1 (en) 2005-08-04
KR101118407B1 (ko) 2012-03-06
EP1709454B1 (de) 2008-07-30

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Legal Events

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