ATE511694T1 - Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern - Google Patents

Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern

Info

Publication number
ATE511694T1
ATE511694T1 AT05708915T AT05708915T ATE511694T1 AT E511694 T1 ATE511694 T1 AT E511694T1 AT 05708915 T AT05708915 T AT 05708915T AT 05708915 T AT05708915 T AT 05708915T AT E511694 T1 ATE511694 T1 AT E511694T1
Authority
AT
Austria
Prior art keywords
bridge defects
memory
data bus
semiconductor memory
resistive bridge
Prior art date
Application number
AT05708915T
Other languages
English (en)
Inventor
Mohamed Azimane
Ananta Majhi
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE511694T1 publication Critical patent/ATE511694T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
AT05708915T 2004-03-05 2005-03-03 Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern ATE511694T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US55052104P 2004-03-05 2004-03-05
US59284404P 2004-07-30 2004-07-30
PCT/IB2005/050778 WO2005088643A1 (en) 2004-03-05 2005-03-03 Method for detecting resistive bridge defects in the global data bus of semiconductor memories

Publications (1)

Publication Number Publication Date
ATE511694T1 true ATE511694T1 (de) 2011-06-15

Family

ID=34960645

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05708915T ATE511694T1 (de) 2004-03-05 2005-03-03 Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern

Country Status (6)

Country Link
EP (1) EP1728254B1 (de)
JP (1) JP2007527090A (de)
KR (1) KR20060133602A (de)
CN (1) CN1930636B (de)
AT (1) ATE511694T1 (de)
WO (1) WO2005088643A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106824833B (zh) * 2017-02-28 2023-07-18 中国振华集团云科电子有限公司 电阻器筛选工艺方法
CN112417191B (zh) * 2019-08-20 2023-09-26 华润微电子（重庆）有限公司 缺陷扫描结果处理方法、装置、系统和存储介质

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2242548B (en) * 1990-03-28 1994-01-12 Sony Corp Testing random access memories
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices

Also Published As

Publication number Publication date
JP2007527090A (ja) 2007-09-20
CN1930636A (zh) 2007-03-14
KR20060133602A (ko) 2006-12-26
CN1930636B (zh) 2012-05-23
EP1728254A1 (de) 2006-12-06
EP1728254B1 (de) 2011-06-01
WO2005088643A1 (en) 2005-09-22

Similar Documents

Publication Publication Date Title
DE60308505D1 (de) Verfahren und system zur automatischen prüfung von software
WO2004003967A3 (en) Scan test method providing real time identification of failing test patterns and test controller for use therewith
WO2007103745A3 (en) At-speed multi-port memory array test method and apparatus
TW200716985A (en) Method for controlling parallelism between probe card and mounting table, storage medium storing inspection program, and inspection apparatus
TW200627923A (en) Testing apparatus and testing method
ATE492885T1 (de) Testvorrichtung für speicher
ATE433158T1 (de) System und verfahren zur erkennung der breite eines datenbusses
DE602005008552D1 (de) Testarchitektur und -verfahren
ATE125386T1 (de) Verfahren und vorrichtung zum internen paralleltest von halbleiterspeichern.
CN100465944C (zh) 一种补偿示波器时基抖动的方法
ATE511694T1 (de) Verfahren zur erkennung resistiver brückendefekte in dem globalen datenbus von halbleiterspeichern
KR20070079030A (ko) 데이터 포맷 방법 및 장치
CN113702798A (zh) 一种边界扫描测试方法、装置、设备、芯片及存储介质
ATE423978T1 (de) System und verfahren für optimierten test und konfigurationsdurchsatz elektronischer schaltungen
TW200603170A (en) Method for detecting resistive bridge defects in the global data bus of semiconductor memories
US7404121B2 (en) Method and machine-readable media for inferring relationships between test results
US8448030B2 (en) Method and apparatus for optimizing address generation for simultaneously running proximity-based BIST algorithms
ATE497241T1 (de) Verfahren und vorrichtung zum erkennen des beginns einer thermischen relaxation in magnetischen datenspeichern
US7626412B2 (en) Adaptive test time reduction for wafer-level testing
US20060098506A1 (en) Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device
ATE487188T1 (de) System und verfahren zur automatischen prüfung von planungsergebnissen
CN115292102B (zh) 仿真方法、电子设备、可读存储介质
JP6190141B2 (ja) 記録装置、記録方法
Vartziotis et al. A branch-&-bound algorithm for TAM optimization in multi-V dd SoCs
ATE408844T1 (de) Testen einer pipeline in einem integrierten schaltkreis

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties