DE602004021927D1 - Halbleiterbauelement und verfahren zu seiner herstellung - Google Patents

Halbleiterbauelement und verfahren zu seiner herstellung

Info

Publication number
DE602004021927D1
DE602004021927D1 DE602004021927T DE602004021927T DE602004021927D1 DE 602004021927 D1 DE602004021927 D1 DE 602004021927D1 DE 602004021927 T DE602004021927 T DE 602004021927T DE 602004021927 T DE602004021927 T DE 602004021927T DE 602004021927 D1 DE602004021927 D1 DE 602004021927D1
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DE
Germany
Prior art keywords
production
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004021927T
Other languages
English (en)
Inventor
Hiroyasu Jobetto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Nippon CMK Corp
CMK Corp
Original Assignee
Casio Computer Co Ltd
Nippon CMK Corp
CMK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd, Nippon CMK Corp, CMK Corp filed Critical Casio Computer Co Ltd
Publication of DE602004021927D1 publication Critical patent/DE602004021927D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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DE602004021927T 2003-12-25 2004-12-21 Halbleiterbauelement und verfahren zu seiner herstellung Active DE602004021927D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003428695 2003-12-25
JP2004107798 2004-03-31
PCT/JP2004/019675 WO2005064641A2 (en) 2003-12-25 2004-12-21 Semiconductor device and method of fabricating the same

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Publication Number Publication Date
DE602004021927D1 true DE602004021927D1 (de) 2009-08-20

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US (2) US7489032B2 (de)
EP (2) EP1901349A3 (de)
KR (1) KR100731842B1 (de)
DE (1) DE602004021927D1 (de)
HK (1) HK1095208A1 (de)
TW (1) TWI250636B (de)
WO (1) WO2005064641A2 (de)

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WO2005064641A3 (en) 2005-11-17
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WO2005064641A2 (en) 2005-07-14
US7867828B2 (en) 2011-01-11
EP1629533B1 (de) 2009-07-08
EP1629533A2 (de) 2006-03-01
US7489032B2 (en) 2009-02-10
TW200527647A (en) 2005-08-16
EP1901349A2 (de) 2008-03-19
EP1901349A3 (de) 2013-12-25
US20080014681A1 (en) 2008-01-17
TWI250636B (en) 2006-03-01
US20050140007A1 (en) 2005-06-30

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