DE60142868D1 - Speichersystem und zugehöriges Programmierverfahren - Google Patents

Speichersystem und zugehöriges Programmierverfahren

Info

Publication number
DE60142868D1
DE60142868D1 DE60142868T DE60142868T DE60142868D1 DE 60142868 D1 DE60142868 D1 DE 60142868D1 DE 60142868 T DE60142868 T DE 60142868T DE 60142868 T DE60142868 T DE 60142868T DE 60142868 D1 DE60142868 D1 DE 60142868D1
Authority
DE
Germany
Prior art keywords
memory system
programming method
associated programming
memory
programming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60142868T
Other languages
English (en)
Inventor
Hideo Kosaka
Akihiko Hashiguchi
Takumi Okaue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE60142868D1 publication Critical patent/DE60142868D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE60142868T 2000-06-12 2001-06-11 Speichersystem und zugehöriges Programmierverfahren Expired - Lifetime DE60142868D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000180761A JP2001357682A (ja) 2000-06-12 2000-06-12 メモリシステムおよびそのプログラム方法

Publications (1)

Publication Number Publication Date
DE60142868D1 true DE60142868D1 (de) 2010-10-07

Family

ID=18681785

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60142868T Expired - Lifetime DE60142868D1 (de) 2000-06-12 2001-06-11 Speichersystem und zugehöriges Programmierverfahren

Country Status (5)

Country Link
US (1) US6426895B2 (de)
EP (1) EP1164596B1 (de)
JP (1) JP2001357682A (de)
KR (1) KR100785872B1 (de)
DE (1) DE60142868D1 (de)

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JP4715024B2 (ja) * 2001-05-08 2011-07-06 セイコーエプソン株式会社 不揮発性半導体記憶装置のプログラム方法
JP2002334588A (ja) * 2001-05-11 2002-11-22 Seiko Epson Corp 不揮発性半導体記憶装置のプログラム方法
US6864529B2 (en) * 2001-08-23 2005-03-08 Hewlett-Packard Development Company, L.P. Thin film transistor memory device
US6987695B2 (en) 2003-03-25 2006-01-17 Promos Technologies Inc. Writing data to nonvolatile memory
US7046551B2 (en) 2003-03-25 2006-05-16 Mosel Vitelic, Inc. Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area
JP4750034B2 (ja) * 2004-07-30 2011-08-17 スパンション エルエルシー 半導体装置および書き込み方法
KR100645043B1 (ko) * 2004-09-08 2006-11-10 삼성전자주식회사 테스트용 버퍼를 구비한 불휘발성 메모리 장치 및 그것의테스트 방법
KR100590219B1 (ko) * 2004-12-01 2006-06-19 삼성전자주식회사 프로그램 시간을 줄일 수 있는 불 휘발성 메모리 장치
WO2007013154A1 (ja) * 2005-07-27 2007-02-01 Spansion Llc 半導体装置およびその制御方法
WO2007069295A1 (ja) 2005-12-13 2007-06-21 Spansion Llc 半導体装置およびその制御方法
JP4908083B2 (ja) * 2006-06-30 2012-04-04 株式会社東芝 メモリコントローラ
KR101320519B1 (ko) 2006-07-27 2013-10-23 삼성전자주식회사 패스 트랜지스터를 갖는 비휘발성 메모리 소자 및 그 동작방법
US7849383B2 (en) * 2007-06-25 2010-12-07 Sandisk Corporation Systems and methods for reading nonvolatile memory using multiple reading schemes
JP5416079B2 (ja) * 2010-12-16 2014-02-12 株式会社日立製作所 半導体記憶装置、およびメモリモジュール
KR102005845B1 (ko) * 2015-03-07 2019-08-01 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 이의 구동 방법
US10121553B2 (en) 2015-09-30 2018-11-06 Sunrise Memory Corporation Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
US9892800B2 (en) 2015-09-30 2018-02-13 Sunrise Memory Corporation Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
US11120884B2 (en) 2015-09-30 2021-09-14 Sunrise Memory Corporation Implementing logic function and generating analog signals using NOR memory strings
US9842651B2 (en) * 2015-11-25 2017-12-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin film transistor strings
FR3043245B1 (fr) * 2015-11-03 2017-10-27 Stmicroelectronics Rousset Procede de lecture d'une memoire eeprom et dispositif correspondant
US10692874B2 (en) 2017-06-20 2020-06-23 Sunrise Memory Corporation 3-dimensional NOR string arrays in segmented stacks
US10608008B2 (en) 2017-06-20 2020-03-31 Sunrise Memory Corporation 3-dimensional nor strings with segmented shared source regions
US11180861B2 (en) 2017-06-20 2021-11-23 Sunrise Memory Corporation 3-dimensional NOR string arrays in segmented stacks
US10608011B2 (en) 2017-06-20 2020-03-31 Sunrise Memory Corporation 3-dimensional NOR memory array architecture and methods for fabrication thereof
US10896916B2 (en) 2017-11-17 2021-01-19 Sunrise Memory Corporation Reverse memory cell
US10622377B2 (en) 2017-12-28 2020-04-14 Sunrise Memory Corporation 3-dimensional NOR memory array with very fine pitch: device and method
US10381378B1 (en) * 2018-02-02 2019-08-13 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin-film transistor strings
US10475812B2 (en) * 2018-02-02 2019-11-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin-film transistor strings
US11069696B2 (en) 2018-07-12 2021-07-20 Sunrise Memory Corporation Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto
US10741581B2 (en) 2018-07-12 2020-08-11 Sunrise Memory Corporation Fabrication method for a 3-dimensional NOR memory array
US11751391B2 (en) 2018-07-12 2023-09-05 Sunrise Memory Corporation Methods for fabricating a 3-dimensional memory structure of nor memory strings
TWI713195B (zh) 2018-09-24 2020-12-11 美商森恩萊斯記憶體公司 三維ｎｏｒ記憶電路製程中之晶圓接合及其形成之積體電路
CN113169041B (zh) 2018-12-07 2024-04-09 日升存储公司 形成多层垂直nor型存储器串阵列的方法
JP7425069B2 (ja) 2019-01-30 2024-01-30 サンライズ メモリー コーポレイション 基板接合を用いた高帯域幅・大容量メモリ組み込み型電子デバイス
US11398492B2 (en) 2019-02-11 2022-07-26 Sunrise Memory Corporation Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays
US11917821B2 (en) 2019-07-09 2024-02-27 Sunrise Memory Corporation Process for a 3-dimensional array of horizontal nor-type memory strings
KR20220031033A (ko) 2019-07-09 2022-03-11 선라이즈 메모리 코포레이션 수평 nor형 메모리 스트링의 3차원 어레이를 위한 공정
WO2021127218A1 (en) 2019-12-19 2021-06-24 Sunrise Memory Corporation Process for preparing a channel region of a thin-film transistor
WO2021159028A1 (en) 2020-02-07 2021-08-12 Sunrise Memory Corporation High capacity memory circuit with low effective latency
CN115362436A (zh) 2020-02-07 2022-11-18 日升存储公司 准易失性系统级存储器
US11507301B2 (en) 2020-02-24 2022-11-22 Sunrise Memory Corporation Memory module implementing memory centric architecture
US11508693B2 (en) 2020-02-24 2022-11-22 Sunrise Memory Corporation High capacity memory module including wafer-section memory circuit
US11561911B2 (en) 2020-02-24 2023-01-24 Sunrise Memory Corporation Channel controller for shared memory access
WO2021207050A1 (en) 2020-04-08 2021-10-14 Sunrise Memory Corporation Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional nor memory string array
WO2022047067A1 (en) * 2020-08-31 2022-03-03 Sunrise Memory Corporation Thin-film storage transistors in a 3-dimensional array or nor memory strings and process for fabricating the same
US11842777B2 (en) 2020-11-17 2023-12-12 Sunrise Memory Corporation Methods for reducing disturb errors by refreshing data alongside programming or erase operations
US11848056B2 (en) 2020-12-08 2023-12-19 Sunrise Memory Corporation Quasi-volatile memory with enhanced sense amplifier operation
TW202310429A (zh) 2021-07-16 2023-03-01 美商日升存儲公司 薄膜鐵電電晶體的三維記憶體串陣列

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US6037785A (en) * 1990-09-20 2000-03-14 Higgins; H. Dan Probe card apparatus
JPH05211338A (ja) * 1991-10-09 1993-08-20 Mitsubishi Electric Corp 不揮発性半導体装置
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US5544103A (en) * 1992-03-03 1996-08-06 Xicor, Inc. Compact page-erasable eeprom non-volatile memory
KR100253868B1 (ko) * 1995-11-13 2000-05-01 니시무로 타이죠 불휘발성 반도체기억장치
US5883826A (en) * 1996-09-30 1999-03-16 Wendell; Dennis Lee Memory block select using multiple word lines to address a single memory cell row

Also Published As

Publication number Publication date
US6426895B2 (en) 2002-07-30
KR100785872B1 (ko) 2007-12-17
EP1164596B1 (de) 2010-08-25
JP2001357682A (ja) 2001-12-26
US20010053092A1 (en) 2001-12-20
EP1164596A2 (de) 2001-12-19
KR20010112089A (ko) 2001-12-20
EP1164596A3 (de) 2005-11-16

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