DE60128561D1 - Digital kontrollierte, analoge Verzögerungsregelschleife - Google Patents
Digital kontrollierte, analoge VerzögerungsregelschleifeInfo
- Publication number
- DE60128561D1 DE60128561D1 DE60128561T DE60128561T DE60128561D1 DE 60128561 D1 DE60128561 D1 DE 60128561D1 DE 60128561 T DE60128561 T DE 60128561T DE 60128561 T DE60128561 T DE 60128561T DE 60128561 D1 DE60128561 D1 DE 60128561D1
- Authority
- DE
- Germany
- Prior art keywords
- locked loop
- digitally controlled
- delay locked
- analogue delay
- controlled analogue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00208—Layout of the delay element using FET's using differential stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00234—Layout of the delay element using circuits having two logic levels
- H03K2005/00241—Layout of the delay element using circuits having two logic levels using shift registers
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/918,583 US6628154B2 (en) | 2001-07-31 | 2001-07-31 | Digitally controlled analog delay locked loop (DLL) |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60128561D1 true DE60128561D1 (de) | 2007-07-05 |
Family
ID=25440616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60128561T Expired - Lifetime DE60128561D1 (de) | 2001-07-31 | 2001-11-23 | Digital kontrollierte, analoge Verzögerungsregelschleife |
Country Status (6)
Country | Link |
---|---|
US (1) | US6628154B2 (de) |
EP (1) | EP1282229B1 (de) |
JP (1) | JP4172570B2 (de) |
KR (1) | KR20030011516A (de) |
DE (1) | DE60128561D1 (de) |
TW (1) | TW538596B (de) |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020184577A1 (en) * | 2001-05-29 | 2002-12-05 | James Chow | Precision closed loop delay line for wide frequency data recovery |
DE10135582C1 (de) * | 2001-07-20 | 2003-01-16 | Infineon Technologies Ag | Justierschaltung und Verfahren zum Abstimmen eines Taktsignals |
US6798259B2 (en) * | 2001-08-03 | 2004-09-28 | Micron Technology, Inc. | System and method to improve the efficiency of synchronous mirror delays and delay locked loops |
JP3966012B2 (ja) * | 2002-02-21 | 2007-08-29 | セイコーエプソン株式会社 | 多相クロック生成回路およびクロック逓倍回路 |
JP2003324348A (ja) * | 2002-04-30 | 2003-11-14 | Elpida Memory Inc | Dll回路 |
KR20040034985A (ko) * | 2002-10-18 | 2004-04-29 | 엘지전자 주식회사 | 클럭신호 생성회로 |
US7336752B2 (en) * | 2002-12-31 | 2008-02-26 | Mosaid Technologies Inc. | Wide frequency range delay locked loop |
KR100531469B1 (ko) * | 2003-01-09 | 2005-11-28 | 주식회사 하이닉스반도체 | 지연고정 정보저장부를 구비한 아날로그 지연고정루프 |
KR100507873B1 (ko) * | 2003-01-10 | 2005-08-17 | 주식회사 하이닉스반도체 | 듀티 보정 회로를 구비한 아날로그 지연고정루프 |
KR100532415B1 (ko) * | 2003-01-10 | 2005-12-02 | 삼성전자주식회사 | 돌발지터 정보를 차단할 수 있는 동기루프 회로 및 이의돌발지터 정보 차단방법 |
US7034596B2 (en) * | 2003-02-11 | 2006-04-25 | Lattice Semiconductor Corporation | Adaptive input logic for phase adjustments |
US7477716B2 (en) | 2003-06-25 | 2009-01-13 | Mosaid Technologies, Inc. | Start up circuit for delay locked loop |
US6812760B1 (en) * | 2003-07-02 | 2004-11-02 | Micron Technology, Inc. | System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits |
US6847241B1 (en) * | 2003-07-25 | 2005-01-25 | Xilinx, Inc. | Delay lock loop using shift register with token bit to select adjacent clock signals |
DE102004004091B4 (de) * | 2004-01-27 | 2008-07-03 | Qimonda Ag | Vorrichtung zur Verwendung bei der Synchronisation von Taktsignalen, sowie Taktsignal-Synchronisationsverfahren |
US7071745B2 (en) * | 2004-02-11 | 2006-07-04 | Promos Technologies, Inc. | Voltage-controlled analog delay locked loop |
JP4583043B2 (ja) * | 2004-02-13 | 2010-11-17 | 凸版印刷株式会社 | 半導体メモリ |
KR100537202B1 (ko) * | 2004-05-06 | 2005-12-16 | 주식회사 하이닉스반도체 | 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자 |
US7421606B2 (en) | 2004-05-18 | 2008-09-02 | Micron Technology, Inc. | DLL phase detection using advanced phase equalization |
ITTO20040460A1 (it) * | 2004-07-07 | 2004-10-07 | Fameccanica Data Spa | Prodotti igienico-sanitario assorbente indossabile a guisa di mutandina e relativo procedimento di fabbricazione. |
US7587012B2 (en) * | 2004-07-08 | 2009-09-08 | Rambus, Inc. | Dual loop clock recovery circuit |
US7078950B2 (en) * | 2004-07-20 | 2006-07-18 | Micron Technology, Inc. | Delay-locked loop with feedback compensation |
US7057429B2 (en) * | 2004-07-20 | 2006-06-06 | Micron Technology, Inc. | Method and apparatus for digital phase generation at high frequencies |
US7138845B2 (en) * | 2004-07-22 | 2006-11-21 | Micron Technology, Inc. | Method and apparatus to set a tuning range for an analog delay |
US7088156B2 (en) * | 2004-08-31 | 2006-08-08 | Micron Technology, Inc. | Delay-locked loop having a pre-shift phase detector |
WO2006033203A1 (ja) * | 2004-09-21 | 2006-03-30 | Advantest Corporation | 遅延ロックループ回路、位相ロックループ回路、タイミング発生器、半導体試験装置及び半導体集積回路 |
US7202719B2 (en) * | 2004-09-30 | 2007-04-10 | Motorola, Inc. | Method and apparatus for frequency synthesis |
KR100632368B1 (ko) * | 2004-11-23 | 2006-10-09 | 삼성전자주식회사 | 락킹속도가 향상되는 내부클락발생회로와 이에 포함되는아날로그 싱크로너스 미러 딜레이 |
US7227395B1 (en) * | 2005-02-09 | 2007-06-05 | Altera Corporation | High-performance memory interface circuit architecture |
US7602859B2 (en) * | 2005-04-28 | 2009-10-13 | Intel Corporation | Calibrating integrating receivers for source synchronous protocol |
US20060245473A1 (en) * | 2005-04-28 | 2006-11-02 | Cheng Roger K | Integrating receivers for source synchronous protocol |
US7355464B2 (en) * | 2005-05-09 | 2008-04-08 | Micron Technology, Inc. | Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency |
US7423919B2 (en) * | 2005-05-26 | 2008-09-09 | Micron Technology, Inc. | Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
US7304516B2 (en) * | 2005-09-01 | 2007-12-04 | Micron Technology, Inc. | Method and apparatus for digital phase generation for high frequency clock applications |
US8085893B2 (en) | 2005-09-13 | 2011-12-27 | Rambus, Inc. | Low jitter clock recovery circuit |
KR100744069B1 (ko) * | 2005-09-28 | 2007-07-30 | 주식회사 하이닉스반도체 | 디지털과 아날로그 제어를 이용한 전압제어지연라인의딜레이 셀 |
US20070096787A1 (en) * | 2005-11-03 | 2007-05-03 | United Memories, Inc. | Method for improving the timing resolution of DLL controlled delay lines |
JP5134779B2 (ja) * | 2006-03-13 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 遅延同期回路 |
US7412617B2 (en) | 2006-04-06 | 2008-08-12 | Mediatek Inc. | Phase frequency detector with limited output pulse width and method thereof |
US7671644B2 (en) * | 2006-05-24 | 2010-03-02 | Micron Technology Inc. | Process insensitive delay line |
US7916824B2 (en) * | 2006-08-18 | 2011-03-29 | Texas Instruments Incorporated | Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique |
KR20080037233A (ko) * | 2006-10-25 | 2008-04-30 | 삼성전자주식회사 | 지연 동기 루프 회로 |
KR100850285B1 (ko) * | 2007-01-11 | 2008-08-04 | 삼성전자주식회사 | 지연고정루프회로 및 그의 제어방법 |
US7863931B1 (en) * | 2007-11-14 | 2011-01-04 | Lattice Semiconductor Corporation | Flexible delay cell architecture |
JP2009141569A (ja) * | 2007-12-05 | 2009-06-25 | Sony Corp | クロック信号生成回路、表示パネルモジュール、撮像デバイス及び電子機器 |
KR100956770B1 (ko) * | 2007-12-10 | 2010-05-12 | 주식회사 하이닉스반도체 | Dll 회로 및 그 제어 방법 |
JP2009177778A (ja) * | 2008-01-25 | 2009-08-06 | Elpida Memory Inc | Dll回路及びこれを用いた半導体装置、並びに、dll回路の制御方法 |
US7816961B2 (en) * | 2008-02-08 | 2010-10-19 | Qimonda North America | System and method for signal adjustment |
US7876137B2 (en) * | 2008-11-20 | 2011-01-25 | Promos Technologies Pte.Ltd. | Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices |
JP2011061457A (ja) * | 2009-09-09 | 2011-03-24 | Elpida Memory Inc | クロック生成回路及びこれを備える半導体装置並びにデータ処理システム |
US8564345B2 (en) * | 2011-04-01 | 2013-10-22 | Intel Corporation | Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments |
JP2013070281A (ja) | 2011-09-22 | 2013-04-18 | Toshiba Corp | Dll回路、逓倍回路、及び半導体記憶装置 |
US9036764B1 (en) | 2012-12-07 | 2015-05-19 | Rambus Inc. | Clock recovery circuit |
DE102014210521A1 (de) * | 2014-06-03 | 2015-12-03 | Continental Teves Ag & Co. Ohg | Jitterkompensation im Taktgenerator eines Drehratensensors |
WO2016196848A1 (en) * | 2015-06-03 | 2016-12-08 | Marvell World Trade Ltd. | Delay locked loop |
US10650481B2 (en) * | 2016-03-24 | 2020-05-12 | Fuji Xerox Co., Ltd. | Image processing device, image processing method, and non-transitory computer readable medium for image processing |
US11043941B2 (en) * | 2018-03-16 | 2021-06-22 | Micron Technology, Inc. | Apparatuses and methods for adjusting a phase mixer circuit |
KR102662555B1 (ko) * | 2019-07-05 | 2024-05-03 | 삼성전자주식회사 | 지연 동기 루프 회로 및 이를 구비하는 반도체 메모리 장치 |
CN114884964A (zh) * | 2022-07-11 | 2022-08-09 | 上海富友支付服务股份有限公司 | 基于Tuxedo架构的业务风控方法和系统 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4330750A (en) | 1979-03-13 | 1982-05-18 | International Computers Limited | Variable delay circuits |
US4833695A (en) | 1987-09-08 | 1989-05-23 | Tektronix, Inc. | Apparatus for skew compensating signals |
US5231319A (en) * | 1991-08-22 | 1993-07-27 | Ncr Corporation | Voltage variable delay circuit |
US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
FR2696061B1 (fr) | 1992-09-22 | 1994-12-02 | Rainard Jean Luc | Procédé pour retarder temporellement un signal et circuit à retard correspondant. |
US5382921A (en) * | 1992-11-23 | 1995-01-17 | National Semiconductor Corporation | Automatic selection of an operating frequency in a low-gain broadband phase lock loop system |
JPH0774596A (ja) * | 1993-08-31 | 1995-03-17 | Mitsubishi Electric Corp | リング発振器 |
JPH08170982A (ja) | 1994-12-19 | 1996-07-02 | Matsushita Electric Ind Co Ltd | ドップラー測位装置 |
US5744991A (en) * | 1995-10-16 | 1998-04-28 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
JP3244162B2 (ja) * | 1996-07-01 | 2002-01-07 | 横河電機株式会社 | Pll回路 |
US6222894B1 (en) | 1996-12-18 | 2001-04-24 | Samsung Electronics Co., Ltd. | Digital delay locked loop for reducing power consumption of synchronous semiconductor memory device |
JPH10285024A (ja) * | 1997-04-07 | 1998-10-23 | Nec Corp | 高速ロックアップ機能付pll回路 |
JP3388134B2 (ja) | 1997-04-10 | 2003-03-17 | 富士通株式会社 | 位相比較回路、dll回路および半導体集積回路 |
JP3750707B2 (ja) | 1997-09-02 | 2006-03-01 | ソニー株式会社 | スペクトラム拡散信号検出方法および装置 |
US6101197A (en) * | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
US6046620A (en) * | 1997-12-18 | 2000-04-04 | Advanced Micro Devices, Inc. | Programmable delay line |
JPH11205102A (ja) | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 遅延同期回路 |
JPH11274904A (ja) | 1998-03-26 | 1999-10-08 | Sanyo Electric Co Ltd | 遅延回路 |
US6157691A (en) | 1998-04-14 | 2000-12-05 | Lsi Logic Corporation | Fully integrated phase-locked loop with resistor-less loop filer |
US6100733A (en) | 1998-06-09 | 2000-08-08 | Siemens Aktiengesellschaft | Clock latency compensation circuit for DDR timing |
US6327318B1 (en) * | 1998-06-30 | 2001-12-04 | Mosaid Technologies Incorporated | Process, voltage, temperature independent switched delay compensation scheme |
CA2263061C (en) * | 1999-02-26 | 2011-01-25 | Ki-Jun Lee | Dual control analog delay element |
JP3380206B2 (ja) * | 1999-03-31 | 2003-02-24 | 沖電気工業株式会社 | 内部クロック発生回路 |
US6242955B1 (en) * | 1999-09-20 | 2001-06-05 | Silicon Magic Corporation | Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal |
US6333959B1 (en) * | 2000-04-25 | 2001-12-25 | Winbond Electronics Corporation | Cross feedback latch-type bi-directional shift register in a delay lock loop circuit |
-
2001
- 2001-07-31 US US09/918,583 patent/US6628154B2/en not_active Expired - Lifetime
- 2001-11-23 DE DE60128561T patent/DE60128561D1/de not_active Expired - Lifetime
- 2001-11-23 EP EP01127404A patent/EP1282229B1/de not_active Expired - Lifetime
- 2001-12-06 JP JP2001372456A patent/JP4172570B2/ja not_active Expired - Fee Related
- 2001-12-25 TW TW090132150A patent/TW538596B/zh not_active IP Right Cessation
-
2002
- 2002-04-30 KR KR1020020023623A patent/KR20030011516A/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2003060501A (ja) | 2003-02-28 |
KR20030011516A (ko) | 2003-02-11 |
EP1282229B1 (de) | 2007-05-23 |
EP1282229A1 (de) | 2003-02-05 |
TW538596B (en) | 2003-06-21 |
US20030025539A1 (en) | 2003-02-06 |
US6628154B2 (en) | 2003-09-30 |
JP4172570B2 (ja) | 2008-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60128561D1 (de) | Digital kontrollierte, analoge Verzögerungsregelschleife | |
TWI319936B (en) | Digital delay locked loop and control method thereof | |
GB0104535D0 (en) | Digital cartesian loop | |
DE60226454D1 (de) | Digitales basisband-system | |
FI20010694A0 (fi) | Implantti | |
DE602004011277D1 (de) | Typ II komplett digitaler Phasenregelkreis | |
HK1070436A1 (en) | High speed auto-tuning loop. | |
AU2002342653A8 (en) | Modified growth hormone | |
MXPA03003642A (es) | Componente de sujecion de rizos hecho de materiales termicamente retraidos. | |
AU2003253203A1 (en) | Phase locked loop | |
DE60229183D1 (de) | Leitschaufel-Verstellantrieb | |
ATE356126T1 (de) | 6,7-dihydro-5h-pyrazolo-1,2-aö pyrazol-1-one zur kontrolle von entzündungsfördernden cytokinen | |
DK1401451T3 (da) | Quinazolinderivater, der fremmer frigivelsen af parathyroidhormon | |
NL1020435A1 (nl) | Heupprothese. | |
DE60206875D1 (de) | Phasenregelschleife | |
GB0230289D0 (en) | Improved phase locked loop | |
AU2003239113A8 (en) | Digital network | |
DE50302923D1 (de) | Digital steuerbarer oszillator | |
DE50302636D1 (de) | Phasenregelkreis | |
DE60214100D1 (de) | Verzögerungsregelschleife | |
AU2003224827A1 (en) | Data-directed frequency-and-phase lock loop | |
AU2002252890A1 (en) | Phase-locked loop system | |
DE69929201D1 (de) | Verbesserte Verzögerungsregelschleife | |
DE60112632T2 (de) | Phasenverriegelungsschleife | |
DE60000750D1 (de) | Phasenregelkreis |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |