DE60214100D1 - Verzögerungsregelschleife - Google Patents

Verzögerungsregelschleife

Info

Publication number
DE60214100D1
DE60214100D1 DE60214100T DE60214100T DE60214100D1 DE 60214100 D1 DE60214100 D1 DE 60214100D1 DE 60214100 T DE60214100 T DE 60214100T DE 60214100 T DE60214100 T DE 60214100T DE 60214100 D1 DE60214100 D1 DE 60214100D1
Authority
DE
Germany
Prior art keywords
locked loop
delay locked
delay
loop
locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60214100T
Other languages
English (en)
Other versions
DE60214100T2 (de
Inventor
Seiichi Watarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE60214100D1 publication Critical patent/DE60214100D1/de
Application granted granted Critical
Publication of DE60214100T2 publication Critical patent/DE60214100T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60214100T 2001-09-17 2002-09-14 Verzögerungsregelschleife Expired - Lifetime DE60214100T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001281115A JP4522623B2 (ja) 2001-09-17 2001-09-17 遅延制御装置
JP2001281115 2001-09-17

Publications (2)

Publication Number Publication Date
DE60214100D1 true DE60214100D1 (de) 2006-10-05
DE60214100T2 DE60214100T2 (de) 2007-04-12

Family

ID=19105002

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60214100T Expired - Lifetime DE60214100T2 (de) 2001-09-17 2002-09-14 Verzögerungsregelschleife

Country Status (4)

Country Link
US (1) US7164743B2 (de)
EP (1) EP1294101B1 (de)
JP (1) JP4522623B2 (de)
DE (1) DE60214100T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3759134B2 (ja) * 2003-08-29 2006-03-22 ローム株式会社 電源装置
KR100540930B1 (ko) 2003-10-31 2006-01-11 삼성전자주식회사 지연동기루프 회로
US7443905B1 (en) * 2004-03-19 2008-10-28 National Semiconductor Corporation Apparatus and method for spread spectrum clock generator with accumulator
JP4774005B2 (ja) * 2007-04-11 2011-09-14 ザインエレクトロニクス株式会社 受信装置
KR100892684B1 (ko) 2007-11-09 2009-04-15 주식회사 하이닉스반도체 데이터 센터 트랙킹 회로 및 이를 포함하는 반도체 집적회로
US8116540B2 (en) * 2008-04-04 2012-02-14 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
JP5807550B2 (ja) * 2012-01-10 2015-11-10 株式会社ソシオネクスト 半導体装置
US9477258B2 (en) 2013-05-22 2016-10-25 Industrial Technology Research Institute Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3558933A (en) * 1968-05-01 1971-01-26 Ampex Voltage variable delay line termination
JP3639000B2 (ja) * 1995-06-13 2005-04-13 富士通株式会社 位相合わせ装置及び遅延制御回路
KR100295052B1 (ko) 1998-09-02 2001-07-12 윤종용 전압제어지연라인의단위지연기들의수를가변시킬수있는제어부를구비하는지연동기루프및이에대한제어방법
FR2792760B1 (fr) * 1999-04-23 2001-08-17 St Microelectronics Sa Memoire a reglage optimise des instants de precharge
JP2000357951A (ja) 1999-06-15 2000-12-26 Mitsubishi Electric Corp 遅延回路、クロック生成回路及び位相同期回路
US6275555B1 (en) * 1999-12-30 2001-08-14 Intel Corporation Digital delay locked loop for adaptive de-skew clock generation
JP3865191B2 (ja) * 2000-02-21 2007-01-10 株式会社ルネサステクノロジ 半導体集積回路装置

Also Published As

Publication number Publication date
US20030053577A1 (en) 2003-03-20
EP1294101A3 (de) 2004-08-04
JP4522623B2 (ja) 2010-08-11
JP2003087114A (ja) 2003-03-20
EP1294101B1 (de) 2006-08-23
US7164743B2 (en) 2007-01-16
DE60214100T2 (de) 2007-04-12
EP1294101A2 (de) 2003-03-19

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