DE69929201D1 - Verbesserte Verzögerungsregelschleife - Google Patents

Verbesserte Verzögerungsregelschleife

Info

Publication number
DE69929201D1
DE69929201D1 DE69929201T DE69929201T DE69929201D1 DE 69929201 D1 DE69929201 D1 DE 69929201D1 DE 69929201 T DE69929201 T DE 69929201T DE 69929201 T DE69929201 T DE 69929201T DE 69929201 D1 DE69929201 D1 DE 69929201D1
Authority
DE
Germany
Prior art keywords
locked loop
delay locked
improved delay
improved
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69929201T
Other languages
English (en)
Inventor
Jesus Guinea
Luciano Tomasini
Santo Maggio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69929201D1 publication Critical patent/DE69929201D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
DE69929201T 1999-10-18 1999-10-18 Verbesserte Verzögerungsregelschleife Expired - Lifetime DE69929201D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99830657A EP1094608B1 (de) 1999-10-18 1999-10-18 Verbesserte Verzögerungsregelschleife

Publications (1)

Publication Number Publication Date
DE69929201D1 true DE69929201D1 (de) 2006-02-02

Family

ID=8243633

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69929201T Expired - Lifetime DE69929201D1 (de) 1999-10-18 1999-10-18 Verbesserte Verzögerungsregelschleife

Country Status (4)

Country Link
US (1) US6414526B1 (de)
EP (1) EP1094608B1 (de)
JP (1) JP2001168711A (de)
DE (1) DE69929201D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271786B1 (de) * 2001-06-28 2005-10-12 STMicroelectronics S.r.l. Verbesserte Verzögerungsregelschleife
CN1393993A (zh) * 2001-07-02 2003-01-29 朗迅科技公司 延迟补偿电路
KR100423012B1 (ko) * 2001-09-28 2004-03-16 주식회사 버카나와이어리스코리아 오(誤)동기 방지 기능을 가진 지연 동기 루프 회로
JP3966012B2 (ja) * 2002-02-21 2007-08-29 セイコーエプソン株式会社 多相クロック生成回路およびクロック逓倍回路
US7839178B2 (en) * 2002-08-20 2010-11-23 Seagate Technology Llc High speed digital phase/frequency comparator for phase locked loops
JP2009147829A (ja) * 2007-12-17 2009-07-02 Panasonic Corp Ｄｌｌ回路，撮像装置，メモリ装置
KR101197462B1 (ko) 2011-05-31 2012-11-09 주식회사 실리콘웍스 오동기 록 방지 회로, 방지 방법 및 그를 이용한 지연고정루프

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3481472D1 (de) * 1984-12-21 1990-04-05 Ibm Digitale phasenregelschleife.
US4847870A (en) * 1987-11-25 1989-07-11 Siemens Transmission Systems, Inc. High resolution digital phase-lock loop circuit
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
EP0460274B1 (de) * 1990-06-08 1995-05-31 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung für einen Phasenkomparator
US5488641A (en) * 1992-12-10 1996-01-30 Northern Telecom Limited Digital phase-locked loop circuit
KR960009965B1 (ko) * 1994-04-14 1996-07-25 금성일렉트론 주식회사 주파수 배수 회로
US5537069A (en) * 1995-03-30 1996-07-16 Intel Corporation Apparatus and method for selecting a tap range in a digital delay line
JP3169794B2 (ja) * 1995-05-26 2001-05-28 日本電気株式会社 遅延クロック生成回路
US5663665A (en) * 1995-11-29 1997-09-02 Cypress Semiconductor Corp. Means for control limits for delay locked loop
US5786715A (en) * 1996-06-21 1998-07-28 Sun Microsystems, Inc. Programmable digital frequency multiplier
US6037812A (en) * 1998-05-18 2000-03-14 National Semiconductor Corporation Delay locked loop (DLL) based clock synthesis
US6255880B1 (en) * 1999-10-25 2001-07-03 Xilinx, Inc. One-shot DLL circuit and method

Also Published As

Publication number Publication date
JP2001168711A (ja) 2001-06-22
EP1094608A1 (de) 2001-04-25
EP1094608B1 (de) 2005-12-28
US6414526B1 (en) 2002-07-02

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Legal Events

Date Code Title Description
8332 No legal effect for de