DE602004011277D1 - Typ II komplett digitaler Phasenregelkreis - Google Patents

Typ II komplett digitaler Phasenregelkreis

Info

Publication number
DE602004011277D1
DE602004011277D1 DE602004011277T DE602004011277T DE602004011277D1 DE 602004011277 D1 DE602004011277 D1 DE 602004011277D1 DE 602004011277 T DE602004011277 T DE 602004011277T DE 602004011277 T DE602004011277 T DE 602004011277T DE 602004011277 D1 DE602004011277 D1 DE 602004011277D1
Authority
DE
Germany
Prior art keywords
type
locked loop
digital phase
complete digital
complete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004011277T
Other languages
English (en)
Other versions
DE602004011277T2 (de
Inventor
Robert B Staszewski
Dirk Leipold
Khurram Muhammad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE602004011277D1 publication Critical patent/DE602004011277D1/de
Application granted granted Critical
Publication of DE602004011277T2 publication Critical patent/DE602004011277T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3282Acting on the phase and the amplitude of the input signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE602004011277T 2003-01-17 2004-01-15 Typ II komplett digitaler Phasenregelkreis Expired - Lifetime DE602004011277T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US44108003P 2003-01-17 2003-01-17
US441080 2003-01-17
US464957 2003-06-19
US10/464,957 US7145399B2 (en) 2002-06-19 2003-06-19 Type-II all-digital phase-locked loop (PLL)

Publications (2)

Publication Number Publication Date
DE602004011277D1 true DE602004011277D1 (de) 2008-03-06
DE602004011277T2 DE602004011277T2 (de) 2009-01-29

Family

ID=32659500

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004011277T Expired - Lifetime DE602004011277T2 (de) 2003-01-17 2004-01-15 Typ II komplett digitaler Phasenregelkreis

Country Status (4)

Country Link
US (3) US7145399B2 (de)
EP (1) EP1443653B1 (de)
DE (1) DE602004011277T2 (de)
TW (1) TWI360949B (de)

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US7684519B2 (en) * 2001-11-14 2010-03-23 Broadcom Corporation Method and system for adjusting DC offset slice point in an RF receiver
US7599662B2 (en) * 2002-04-29 2009-10-06 Broadcom Corporation Method and system for frequency feedback adjustment in digital receivers
DE602005011464D1 (de) * 2004-10-05 2009-01-15 Azonix Drahtlose kommunikation unter verwendung eines intrinsisch sicheren entwurfs zur verwendung in einem gefährlichen gebiet
US8194792B2 (en) * 2005-01-05 2012-06-05 Agere Systems Inc. Look-ahead digital loop filter for clock and data recovery
US7643803B2 (en) * 2005-06-29 2010-01-05 Intel Corporation Power estimation of a transmission
DE102005030949B3 (de) * 2005-06-30 2006-09-21 Infineon Technologies Ag Verfahren und Vorrichtung zur Stabilisierung einer Übertragungsfunktion eines digitalen Phasenregelkreises
US7403073B2 (en) 2005-09-30 2008-07-22 International Business Machines Corporation Phase locked loop and method for adjusting the frequency and phase in the phase locked loop
DE102005050621B4 (de) * 2005-10-21 2011-06-01 Infineon Technologies Ag Phasenregelkreis und Verfahren zum Betrieb eines Phasenregelkreises
GB0622941D0 (en) 2006-11-17 2006-12-27 Zarlink Semiconductor Inc An asynchronous phase acquisition unit with dithering
GB0622948D0 (en) 2006-11-17 2006-12-27 Zarlink Semiconductor Inc A digital phase locked loop
US8170169B2 (en) * 2006-12-01 2012-05-01 Snowbush Inc. Serializer deserializer circuits
FR2912572A1 (fr) 2007-02-08 2008-08-15 St Microelectronics Sa Procede d'ajout d'un bruit aleatoire dans un circuit convertisseur temps-numerique et circuits pour mettre en oeuvre le procede
US8830001B2 (en) * 2007-06-22 2014-09-09 Texas Instruments Incorporated Low power all digital PLL architecture
US8045670B2 (en) * 2007-06-22 2011-10-25 Texas Instruments Incorporated Interpolative all-digital phase locked loop
US8193866B2 (en) * 2007-10-16 2012-06-05 Mediatek Inc. All-digital phase-locked loop
US7888947B2 (en) * 2007-11-21 2011-02-15 Teradyne, Inc. Calibrating automatic test equipment
TWI358204B (en) * 2007-12-12 2012-02-11 Ind Tech Res Inst All digital phase lock loop and method for control
CN101471657B (zh) * 2007-12-26 2012-05-02 财团法人工业技术研究院 全数字锁相回路以及锁相回路控制方法
GB0800251D0 (en) * 2008-01-08 2008-02-13 Zarlink Semiconductor Inc Phase locked loop with adaptive filter for dco synchronization
TWI368398B (en) * 2008-03-05 2012-07-11 Tse Hsien Yeh Phase lock loop apparatus
CN101594146B (zh) * 2008-05-29 2011-08-24 中芯国际集成电路制造(北京)有限公司 锁相环电路
US8126401B2 (en) * 2008-06-30 2012-02-28 Texas Instruments Incorporated Transmitter PLL with bandwidth on demand
TWI360950B (en) 2008-10-09 2012-03-21 Univ Nat Chiao Tung Digital loop filter for all-digital phase-locked l
US7961038B2 (en) * 2008-12-08 2011-06-14 Electronics And Telecommunications Research Institute Digital proportional integral loop filter
WO2010081188A1 (en) * 2009-01-13 2010-07-22 Locata Corporation Pty Ltd Method and apparatus for extending the range for tracking errors in phase lock loops
GB2470468A (en) * 2009-05-20 2010-11-24 Xintronix Ltd Digitally implemented integral control path in PLL with integrating capacitor
US8058917B2 (en) 2009-06-12 2011-11-15 Infineon Technologies Ag Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping
TWI416876B (zh) * 2009-07-22 2013-11-21 Realtek Semiconductor Corp 頻率相位調整裝置及其相關方法
US7994829B2 (en) * 2009-10-16 2011-08-09 Realtek Semiconductor Corp. Fast lock-in all-digital phase-locked loop with extended tracking range
US8217696B2 (en) 2009-12-17 2012-07-10 Intel Corporation Adaptive digital phase locked loop
TWI474624B (zh) * 2010-07-20 2015-02-21 Etron Technology Inc 雙迴路控制的鎖相迴路
US8711983B2 (en) * 2010-10-29 2014-04-29 Texas Instruments Incorporated Phase locking loop
US8570107B2 (en) 2011-04-01 2013-10-29 Mediatek Singapore Pte. Ltd. Clock generating apparatus and frequency calibrating method of the clock generating apparatus
US8493113B2 (en) 2011-09-12 2013-07-23 International Business Machines Corporation PLL bandwidth correction with offset compensation
US8698567B2 (en) 2012-04-02 2014-04-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Phase-locked loop calibration system and method
US9455728B2 (en) 2014-04-04 2016-09-27 International Business Machines Corporation Digital phase locked loop for low jitter applications
US9941891B2 (en) 2015-06-01 2018-04-10 University Of Southern California Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit
US10727848B2 (en) 2015-07-08 2020-07-28 Analog Devices Global Phase-locked loop having a multi-band oscillator and method for calibrating same
US9778383B2 (en) 2015-09-16 2017-10-03 Siemens Medical Solutions Usa, Inc. Transmission of PET-signals by means of time division multiplexing
CN105553471B (zh) * 2015-12-15 2018-09-25 成都九洲迪飞科技有限责任公司 高灵敏度数字锁相环
US9853807B2 (en) * 2016-04-21 2017-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Automatic detection of change in PLL locking trend
US10359995B2 (en) 2016-04-29 2019-07-23 Texas Instruments Incorporated Architecture and instruction set to support integer division
US10635395B2 (en) 2016-06-30 2020-04-28 Texas Instruments Incorporated Architecture and instruction set to support interruptible floating point division
US9628262B1 (en) 2016-07-19 2017-04-18 Texas Instruments Incorporated Spur reduction in phase locked loops using reference clock dithering
US10295580B2 (en) 2016-10-03 2019-05-21 Analog Devices Global On-chip measurement for phase-locked loop
EP3316484A1 (de) * 2016-10-27 2018-05-02 NXP USA, Inc. Digitaler synthesizer, kommunikationseinheit und verfahren dafür
US11165414B2 (en) * 2019-12-20 2021-11-02 Infineon Technologies Ag Reconfigurable filter network with shortened settling time
KR20220153172A (ko) 2021-05-10 2022-11-18 삼성전자주식회사 위상 고정 루프 및 위상 고정 루프의 동작 방법
TWI762328B (zh) * 2021-05-24 2022-04-21 穩脈科技股份有限公司 分數除頻電路之補償電路

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EP0590323B1 (de) 1992-10-02 1999-06-02 Siemens Schweiz AG Filter zur Einstellung der Bandbreite eines Regelkreises
US5373255A (en) * 1993-07-28 1994-12-13 Motorola, Inc. Low-power, jitter-compensated phase locked loop and method therefor
US5966416A (en) 1996-11-21 1999-10-12 Dsp Group, Inc. Verification of PN synchronization in a spread-spectrum communications receiver
JP3403365B2 (ja) 1999-12-13 2003-05-06 松下電器産業株式会社 クロック抽出回路
US6809598B1 (en) * 2000-10-24 2004-10-26 Texas Instruments Incorporated Hybrid of predictive and closed-loop phase-domain digital PLL architecture
US6813111B2 (en) * 2000-11-24 2004-11-02 Texas Instruments Incorporated Implementation method of digital phase-locked loop
US6851493B2 (en) 2000-12-01 2005-02-08 Texas Instruments Incorporated Digital PLL with gear shift
GB2383697A (en) * 2001-12-27 2003-07-02 Zarlink Semiconductor Inc Method of speeding lock of PLL

Also Published As

Publication number Publication date
TW200428782A (en) 2004-12-16
EP1443653B1 (de) 2008-01-16
US20060290435A1 (en) 2006-12-28
US20050212606A1 (en) 2005-09-29
TWI360949B (en) 2012-03-21
US7382200B2 (en) 2008-06-03
US7463873B2 (en) 2008-12-09
US7145399B2 (en) 2006-12-05
US20030234693A1 (en) 2003-12-25
EP1443653A1 (de) 2004-08-04
DE602004011277T2 (de) 2009-01-29

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