DE60102376D1 - Verfahren zur herstellung einer schicht in einem integrierten schaltkreis mit feinen und breiten strukturen - Google Patents

Verfahren zur herstellung einer schicht in einem integrierten schaltkreis mit feinen und breiten strukturen

Info

Publication number
DE60102376D1
DE60102376D1 DE60102376T DE60102376T DE60102376D1 DE 60102376 D1 DE60102376 D1 DE 60102376D1 DE 60102376 T DE60102376 T DE 60102376T DE 60102376 T DE60102376 T DE 60102376T DE 60102376 D1 DE60102376 D1 DE 60102376D1
Authority
DE
Germany
Prior art keywords
fine
producing
layer
integrated circuit
wide structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60102376T
Other languages
English (en)
Other versions
DE60102376T2 (de
Inventor
Simon Deleonibus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of DE60102376D1 publication Critical patent/DE60102376D1/de
Application granted granted Critical
Publication of DE60102376T2 publication Critical patent/DE60102376T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0277—Electrolithographic processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
DE60102376T 2000-06-16 2001-06-14 Verfahren zur herstellung einer schicht in einem integrierten schaltkreis mit feinen und breiten strukturen Expired - Lifetime DE60102376T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0007718A FR2810447B1 (fr) 2000-06-16 2000-06-16 Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
FR0007718 2000-06-16
PCT/FR2001/001850 WO2001096957A1 (fr) 2000-06-16 2001-06-14 Procede de creation d'un etage de circuit integre ou coexistent des motifs fins et larges

Publications (2)

Publication Number Publication Date
DE60102376D1 true DE60102376D1 (de) 2004-04-22
DE60102376T2 DE60102376T2 (de) 2005-02-24

Family

ID=8851345

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60102376T Expired - Lifetime DE60102376T2 (de) 2000-06-16 2001-06-14 Verfahren zur herstellung einer schicht in einem integrierten schaltkreis mit feinen und breiten strukturen

Country Status (6)

Country Link
US (1) US6727179B2 (de)
EP (1) EP1290498B1 (de)
JP (1) JP4680477B2 (de)
DE (1) DE60102376T2 (de)
FR (1) FR2810447B1 (de)
WO (1) WO2001096957A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664173B2 (en) * 2002-01-09 2003-12-16 Intel Corporation Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control
FR2870043B1 (fr) 2004-05-07 2006-11-24 Commissariat Energie Atomique Fabrication de zones actives de natures differentes directement sur isolant et application au transistor mos a simple ou double grille
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
KR100641980B1 (ko) * 2004-12-17 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 배선 및 그 형성방법
DE102005010550B4 (de) * 2005-03-04 2007-03-22 Neoperl Gmbh Sanitärer Wasserauslauf
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
CN103390584A (zh) * 2012-05-09 2013-11-13 中国科学院微电子研究所 半导体器件的制造方法
KR101421789B1 (ko) * 2012-05-31 2014-07-22 주식회사 엘지화학 패턴의 제조방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4299680A (en) * 1979-12-31 1981-11-10 Texas Instruments Incorporated Method of fabricating magnetic bubble memory device having planar overlay pattern of magnetically soft material
US4612274A (en) * 1985-11-18 1986-09-16 Motorola, Inc. Electron beam/optical hybrid lithographic resist process in acoustic wave devices
JPH02262319A (ja) * 1989-04-03 1990-10-25 Toshiba Corp パターン形成方法
JPH05343535A (ja) * 1992-06-04 1993-12-24 Nec Corp 微細配線の形成方法
JP3263870B2 (ja) * 1993-04-20 2002-03-11 ソニー株式会社 微細パターン導電層を有する半導体装置の製造方法
US5891784A (en) * 1993-11-05 1999-04-06 Lucent Technologies, Inc. Transistor fabrication method
US5545588A (en) * 1995-05-05 1996-08-13 Taiwan Semiconductor Manufacturing Company Method of using disposable hard mask for gate critical dimension control
JP3607022B2 (ja) * 1995-12-11 2005-01-05 株式会社東芝 半導体装置の製造方法
US5916733A (en) * 1995-12-11 1999-06-29 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device
JP3392616B2 (ja) * 1996-01-31 2003-03-31 株式会社東芝 半導体装置の製造方法
US5776821A (en) * 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US5966618A (en) * 1998-03-06 1999-10-12 Advanced Micro Devices, Inc. Method of forming dual field isolation structures
US6416933B1 (en) * 1999-04-01 2002-07-09 Advanced Micro Devices, Inc. Method to produce small space pattern using plasma polymerization layer
JP2001168191A (ja) * 1999-12-13 2001-06-22 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
US6720249B1 (en) * 2000-04-17 2004-04-13 International Business Machines Corporation Protective hardmask for producing interconnect structures
DE50111643D1 (de) * 2000-04-28 2007-01-25 Pes Ges Fuer Medizinische Diag Verfahren zur ermittlung signifikanter knochendichteverluste
US6350695B1 (en) * 2000-06-16 2002-02-26 Chartered Semiconductor Manufacturing Ltd. Pillar process for copper interconnect scheme
US6482726B1 (en) * 2000-10-17 2002-11-19 Advanced Micro Devices, Inc. Control trimming of hard mask for sub-100 nanometer transistor gate
US6429052B1 (en) * 2000-11-13 2002-08-06 Advanced Micro Devices, Inc. Method of making high performance transistor with a reduced width gate electrode and device comprising same
JP2002324787A (ja) * 2001-04-26 2002-11-08 Mitsubishi Electric Corp 半導体装置の製造方法
US6521138B2 (en) * 2001-06-01 2003-02-18 Silicon Integrated Systems Corporation Method for measuring width of bottom under cut during etching process

Also Published As

Publication number Publication date
US20030077899A1 (en) 2003-04-24
US6727179B2 (en) 2004-04-27
FR2810447B1 (fr) 2003-09-05
EP1290498B1 (de) 2004-03-17
JP2004503927A (ja) 2004-02-05
JP4680477B2 (ja) 2011-05-11
DE60102376T2 (de) 2005-02-24
WO2001096957A1 (fr) 2001-12-20
FR2810447A1 (fr) 2001-12-21
EP1290498A1 (de) 2003-03-12

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