DE60045375D1 - Verfahren zur ätzung einer schicht mit niedriger dielektrizitätskonstante - Google Patents
Verfahren zur ätzung einer schicht mit niedriger dielektrizitätskonstanteInfo
- Publication number
- DE60045375D1 DE60045375D1 DE60045375T DE60045375T DE60045375D1 DE 60045375 D1 DE60045375 D1 DE 60045375D1 DE 60045375 T DE60045375 T DE 60045375T DE 60045375 T DE60045375 T DE 60045375T DE 60045375 D1 DE60045375 D1 DE 60045375D1
- Authority
- DE
- Germany
- Prior art keywords
- oxizing
- layer
- dielectric constant
- low dielectric
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13264599P | 1999-05-05 | 1999-05-05 | |
US09/347,582 US6696366B1 (en) | 1998-08-17 | 1999-06-30 | Technique for etching a low capacitance dielectric layer |
PCT/US2000/012356 WO2000067308A1 (en) | 1999-05-05 | 2000-05-04 | Techniques for etching a low capacitance dielectric layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60045375D1 true DE60045375D1 (de) | 2011-01-27 |
Family
ID=26830592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60045375T Expired - Lifetime DE60045375D1 (de) | 1999-05-05 | 2000-05-04 | Verfahren zur ätzung einer schicht mit niedriger dielektrizitätskonstante |
Country Status (7)
Country | Link |
---|---|
US (1) | US6696366B1 (de) |
EP (1) | EP1186014B1 (de) |
JP (1) | JP4657458B2 (de) |
KR (1) | KR100778259B1 (de) |
DE (1) | DE60045375D1 (de) |
TW (1) | TW468224B (de) |
WO (1) | WO2000067308A1 (de) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9904427D0 (en) | 1999-02-26 | 1999-04-21 | Trikon Holdings Ltd | Method treating an insulating layer |
JP3403372B2 (ja) | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
JP3403374B2 (ja) | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
JP3403373B2 (ja) | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
US6777344B2 (en) * | 2001-02-12 | 2004-08-17 | Lam Research Corporation | Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications |
US6620733B2 (en) | 2001-02-12 | 2003-09-16 | Lam Research Corporation | Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics |
US7311852B2 (en) | 2001-03-30 | 2007-12-25 | Lam Research Corporation | Method of plasma etching low-k dielectric materials |
WO2003085717A1 (fr) * | 2002-04-08 | 2003-10-16 | Tokyo Electron Limited | Procede de gravure au plasma |
US20040084411A1 (en) * | 2002-10-31 | 2004-05-06 | Applied Materials, Inc. | Method of etching a silicon-containing dielectric material |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
JP2005033027A (ja) * | 2003-07-07 | 2005-02-03 | Ulvac Japan Ltd | 低誘電率層間絶縁膜のドライエッチング方法 |
US7320927B2 (en) * | 2003-10-20 | 2008-01-22 | Texas Instruments Incorporated | In situ hardmask pullback using an in situ plasma resist trim process |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
JP4643916B2 (ja) * | 2004-03-02 | 2011-03-02 | 株式会社アルバック | 層間絶縁膜のドライエッチング方法及びその装置 |
JP4651956B2 (ja) * | 2004-03-03 | 2011-03-16 | 株式会社アルバック | 層間絶縁膜のドライエッチング方法 |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7579280B2 (en) * | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
JP2006222156A (ja) | 2005-02-08 | 2006-08-24 | Toshiba Corp | 有機膜加工方法 |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) * | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
KR100691011B1 (ko) * | 2005-06-30 | 2007-03-09 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US7402875B2 (en) * | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
US8177990B2 (en) * | 2006-03-31 | 2012-05-15 | Tokyo Electron Limited | Etching method, plasma processing system and storage medium |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US20080157225A1 (en) * | 2006-12-29 | 2008-07-03 | Suman Datta | SRAM and logic transistors with variable height multi-gate transistor architecture |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8809185B1 (en) * | 2013-07-29 | 2014-08-19 | Tokyo Electron Limited | Dry etching method for metallization pattern profiling |
US9355893B1 (en) * | 2015-01-20 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for preventing extreme low-K (ELK) dielectric layer from being damaged during plasma process |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57186335A (en) * | 1981-05-12 | 1982-11-16 | Nippon Telegr & Teleph Corp <Ntt> | Forming method for pattern |
JPS6425419A (en) | 1987-07-21 | 1989-01-27 | Matsushita Electric Ind Co Ltd | Etching |
JPS6459820A (en) | 1987-08-31 | 1989-03-07 | Tokuda Seisakusho | Dry etching |
US5122225A (en) * | 1990-11-21 | 1992-06-16 | Texas Instruments Incorporated | Selective etch method |
DE4107006A1 (de) * | 1991-03-05 | 1992-09-10 | Siemens Ag | Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen |
US5463322A (en) * | 1993-12-03 | 1995-10-31 | General Electric Company | Method of locating common electrode shorts in an imager assembly |
US5545289A (en) * | 1994-02-03 | 1996-08-13 | Applied Materials, Inc. | Passivating, stripping and corrosion inhibition of semiconductor substrates |
US5648296A (en) * | 1994-07-27 | 1997-07-15 | General Electric Company | Post-fabrication repair method for thin film imager devices |
US5654232A (en) * | 1994-08-24 | 1997-08-05 | Intel Corporation | Wetting layer sidewalls to promote copper reflow into grooves |
WO1996019826A1 (en) | 1994-12-20 | 1996-06-27 | National Semiconductor Corporation | A method of fabricating integrated circuits using bilayer dielectrics |
EP0804806A1 (de) * | 1994-12-22 | 1997-11-05 | Benedict G. Pace | Invertiertes chip modul hoher packungsdichte |
US5798909A (en) * | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
US5569356A (en) | 1995-05-19 | 1996-10-29 | Lam Research Corporation | Electrode clamping assembly and method for assembly and use thereof |
US5534751A (en) | 1995-07-10 | 1996-07-09 | Lam Research Corporation | Plasma etching apparatus utilizing plasma confinement |
US5641712A (en) * | 1995-08-07 | 1997-06-24 | Motorola, Inc. | Method and structure for reducing capacitance between interconnect lines |
US5843847A (en) * | 1996-04-29 | 1998-12-01 | Applied Materials, Inc. | Method for etching dielectric layers with high selectivity and low microloading |
JPH10256240A (ja) * | 1997-01-10 | 1998-09-25 | Sony Corp | 半導体装置の製造方法 |
US5783493A (en) * | 1997-01-27 | 1998-07-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for reducing precipitate defects using a plasma treatment post BPSG etchback |
JP3959790B2 (ja) * | 1997-08-26 | 2007-08-15 | ソニー株式会社 | 半導体装置の製造方法 |
EP0911697A3 (de) * | 1997-10-22 | 1999-09-15 | Interuniversitair Microelektronica Centrum Vzw | Fluorierte harte Maske für die Mikrostrukturierung von Polymeren |
US6114250A (en) | 1998-08-17 | 2000-09-05 | Lam Research Corporation | Techniques for etching a low capacitance dielectric layer on a substrate |
FR2789804B1 (fr) * | 1999-02-17 | 2002-08-23 | France Telecom | Procede de gravure anisotrope par plasma gazeux d'un materiau polymere dielectrique organique et application a la microelectronique |
-
1999
- 1999-06-30 US US09/347,582 patent/US6696366B1/en not_active Expired - Lifetime
-
2000
- 2000-05-02 TW TW089108311A patent/TW468224B/zh not_active IP Right Cessation
- 2000-05-04 KR KR1020017013691A patent/KR100778259B1/ko active IP Right Grant
- 2000-05-04 WO PCT/US2000/012356 patent/WO2000067308A1/en active Application Filing
- 2000-05-04 JP JP2000616058A patent/JP4657458B2/ja not_active Expired - Fee Related
- 2000-05-04 DE DE60045375T patent/DE60045375D1/de not_active Expired - Lifetime
- 2000-05-04 EP EP00930416A patent/EP1186014B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP4657458B2 (ja) | 2011-03-23 |
JP2002543613A (ja) | 2002-12-17 |
TW468224B (en) | 2001-12-11 |
WO2000067308A1 (en) | 2000-11-09 |
KR100778259B1 (ko) | 2007-11-22 |
EP1186014B1 (de) | 2010-12-15 |
EP1186014A1 (de) | 2002-03-13 |
US6696366B1 (en) | 2004-02-24 |
KR20010112464A (ko) | 2001-12-20 |
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