DE60127767D1 - Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis - Google Patents
Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten SchaltkreisInfo
- Publication number
- DE60127767D1 DE60127767D1 DE60127767T DE60127767T DE60127767D1 DE 60127767 D1 DE60127767 D1 DE 60127767D1 DE 60127767 T DE60127767 T DE 60127767T DE 60127767 T DE60127767 T DE 60127767T DE 60127767 D1 DE60127767 D1 DE 60127767D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- interconnect structures
- metallized interconnect
- making metallized
- making
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/593,967 US6635566B1 (en) | 2000-06-15 | 2000-06-15 | Method of making metallization and contact structures in an integrated circuit |
US593967 | 2000-06-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60127767D1 true DE60127767D1 (de) | 2007-05-24 |
DE60127767T2 DE60127767T2 (de) | 2007-12-27 |
Family
ID=24376952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60127767T Expired - Fee Related DE60127767T2 (de) | 2000-06-15 | 2001-06-14 | Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis |
Country Status (7)
Country | Link |
---|---|
US (2) | US6635566B1 (de) |
EP (1) | EP1168434B1 (de) |
JP (1) | JP3637000B2 (de) |
KR (1) | KR100421154B1 (de) |
DE (1) | DE60127767T2 (de) |
SG (1) | SG99903A1 (de) |
TW (1) | TW580753B (de) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6635566B1 (en) * | 2000-06-15 | 2003-10-21 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit |
US7183222B2 (en) * | 2000-09-01 | 2007-02-27 | Cypress Semiconductor Corporation | Dual damascene structure and method of making |
KR100469163B1 (ko) * | 2001-03-26 | 2005-02-02 | 가부시끼가이샤 도시바 | 양극활성물질 및 비수전해질 이차전지 |
JP2005508078A (ja) * | 2001-10-31 | 2005-03-24 | 東京エレクトロン株式会社 | 高アスペクト比形態のエッチング方法 |
DE10201448A1 (de) * | 2002-01-16 | 2003-07-24 | Infineon Technologies Ag | Durchgangskontakt und Verfahren zum Herstellen desselben |
US7078334B1 (en) * | 2002-06-06 | 2006-07-18 | Cypress Semiconductor Corporation | In situ hard mask approach for self-aligned contact etch |
US6751125B2 (en) | 2002-11-04 | 2004-06-15 | Freescale Semiconductor, Inc. | Gate voltage reduction in a memory read |
KR100878498B1 (ko) * | 2002-12-30 | 2009-01-15 | 주식회사 하이닉스반도체 | 트랜지스터 제조방법 |
KR100478498B1 (ko) * | 2003-01-30 | 2005-03-28 | 동부아남반도체 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100485388B1 (ko) * | 2003-02-28 | 2005-04-27 | 삼성전자주식회사 | 트렌치 형성 방법 및 이를 이용한 반도체 장치의 제조 방법 |
TW200527485A (en) * | 2004-01-30 | 2005-08-16 | Semiconductor Leading Edge Tec | Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device |
KR100613392B1 (ko) * | 2004-12-23 | 2006-08-17 | 동부일렉트로닉스 주식회사 | 자기 정렬 콘택홀 형성 방법 |
US7429524B2 (en) * | 2005-09-14 | 2008-09-30 | Texas Instruments Incorporated | Transistor design self-aligned to contact |
US20080116494A1 (en) * | 2006-11-20 | 2008-05-22 | Matthias Goldbach | Method for manufacturing a semiconductor device |
US7786019B2 (en) * | 2006-12-18 | 2010-08-31 | Applied Materials, Inc. | Multi-step photomask etching with chlorine for uniformity control |
US7858513B2 (en) * | 2007-06-18 | 2010-12-28 | Organicid, Inc. | Fabrication of self-aligned via holes in polymer thin films |
US7888169B2 (en) * | 2007-12-26 | 2011-02-15 | Organicid, Inc. | Organic semiconductor device and method of manufacturing the same |
DE102010028458A1 (de) * | 2010-04-30 | 2011-11-03 | Globalfoundries Dresden Module One Llc & Co. Kg | Halbleiterbauelement mit Kontaktelementen und Metallsilizidgebieten, die in einer gemeinsamen Prozesssequenz hergestellt sind |
US9048296B2 (en) | 2011-02-11 | 2015-06-02 | International Business Machines Corporation | Method to fabricate copper wiring structures and structures formed thereby |
US9034703B2 (en) | 2012-09-13 | 2015-05-19 | International Business Machines Corporation | Self aligned contact with improved robustness |
US8728927B1 (en) * | 2012-12-10 | 2014-05-20 | International Business Machines Corporation | Borderless contacts for semiconductor transistors |
US10593767B2 (en) * | 2013-12-23 | 2020-03-17 | Chun Wai NG | Field plate structure for power semiconductor device and manufacturing method thereof |
US9478508B1 (en) * | 2015-06-08 | 2016-10-25 | Raytheon Company | Microwave integrated circuit (MMIC) damascene electrical interconnect for microwave energy transmission |
DE102015112135B4 (de) * | 2015-07-24 | 2023-04-06 | Kennametal Inc. | Verdampferkörper mit Titanhydridbeschichtung, Verfahren zu dessen Herstellung und Verwendung |
US10163797B2 (en) * | 2015-10-09 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming interlayer dielectric material by spin-on metal oxide deposition |
US9704754B1 (en) * | 2016-09-22 | 2017-07-11 | International Business Machines Corporation | Self-aligned spacer for cut-last transistor fabrication |
US10510851B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance contact method and structure |
US10522644B1 (en) | 2018-06-21 | 2019-12-31 | Globalfoundries Inc. | Different upper and lower spacers for contact |
US10685869B2 (en) * | 2018-10-19 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of forming the same |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
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US4789648A (en) | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4954142A (en) | 1989-03-07 | 1990-09-04 | International Business Machines Corporation | Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor |
US4933743A (en) | 1989-03-11 | 1990-06-12 | Fairchild Semiconductor Corporation | High performance interconnect system for an integrated circuit |
JPH03198327A (ja) * | 1989-12-26 | 1991-08-29 | Fujitsu Ltd | 半導体装置の製造方法 |
US5093279A (en) | 1991-02-01 | 1992-03-03 | International Business Machines Corporation | Laser ablation damascene process |
US5262354A (en) | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5292689A (en) | 1992-09-04 | 1994-03-08 | International Business Machines Corporation | Method for planarizing semiconductor structure using subminimum features |
US5312777A (en) | 1992-09-25 | 1994-05-17 | International Business Machines Corporation | Fabrication methods for bidirectional field emission devices and storage structures |
US5371047A (en) | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
US5397741A (en) | 1993-03-29 | 1995-03-14 | International Business Machines Corporation | Process for metallized vias in polyimide |
JP3297220B2 (ja) * | 1993-10-29 | 2002-07-02 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
JP2765478B2 (ja) * | 1994-03-30 | 1998-06-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5496771A (en) | 1994-05-19 | 1996-03-05 | International Business Machines Corporation | Method of making overpass mask/insulator for local interconnects |
JP3555333B2 (ja) * | 1996-05-30 | 2004-08-18 | ソニー株式会社 | 半導体装置の製造方法 |
US5726100A (en) * | 1996-06-27 | 1998-03-10 | Micron Technology, Inc. | Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask |
US6010955A (en) * | 1996-09-23 | 2000-01-04 | Kabushiki Kaisha Toshiba | Electrical connection forming process for semiconductor devices |
JPH11145305A (ja) * | 1997-11-07 | 1999-05-28 | Toshiba Corp | 半導体装置の製造方法 |
KR19990062003A (ko) | 1997-12-31 | 1999-07-26 | 김영환 | 반도체장치의 다층 금속배선 형성방법 |
JPH11220025A (ja) * | 1998-02-03 | 1999-08-10 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US6080661A (en) * | 1998-05-29 | 2000-06-27 | Philips Electronics North America Corp. | Methods for fabricating gate and diffusion contacts in self-aligned contact processes |
US6121098A (en) * | 1998-06-30 | 2000-09-19 | Infineon Technologies North America Corporation | Semiconductor manufacturing method |
US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
US6180472B1 (en) * | 1998-07-28 | 2001-01-30 | Matsushita Electrons Corporation | Method for fabricating semiconductor device |
JP3301994B2 (ja) * | 1998-07-28 | 2002-07-15 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP2000091440A (ja) * | 1998-09-08 | 2000-03-31 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6228758B1 (en) * | 1998-10-14 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
JP2000164707A (ja) * | 1998-11-27 | 2000-06-16 | Sony Corp | 半導体装置およびその製造方法 |
US6287951B1 (en) * | 1998-12-07 | 2001-09-11 | Motorola Inc. | Process for forming a combination hardmask and antireflective layer |
JP2001244347A (ja) * | 2000-02-29 | 2001-09-07 | Seiko Epson Corp | 半導体装置およびその製造方法 |
US6544850B1 (en) * | 2000-04-19 | 2003-04-08 | Infineon Technologies Ag | Dynamic random access memory |
US6635566B1 (en) * | 2000-06-15 | 2003-10-21 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit |
US6399512B1 (en) * | 2000-06-15 | 2002-06-04 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer |
-
2000
- 2000-06-15 US US09/593,967 patent/US6635566B1/en not_active Expired - Lifetime
-
2001
- 2001-05-25 SG SG200103139A patent/SG99903A1/en unknown
- 2001-06-14 DE DE60127767T patent/DE60127767T2/de not_active Expired - Fee Related
- 2001-06-14 KR KR10-2001-0033430A patent/KR100421154B1/ko not_active IP Right Cessation
- 2001-06-14 EP EP01401542A patent/EP1168434B1/de not_active Expired - Lifetime
- 2001-06-15 JP JP2001181502A patent/JP3637000B2/ja not_active Expired - Fee Related
- 2001-06-15 TW TW090114590A patent/TW580753B/zh not_active IP Right Cessation
-
2003
- 2003-10-21 US US10/689,034 patent/US20040082182A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP1168434A3 (de) | 2003-11-05 |
KR100421154B1 (ko) | 2004-03-03 |
EP1168434A2 (de) | 2002-01-02 |
DE60127767T2 (de) | 2007-12-27 |
JP2002016139A (ja) | 2002-01-18 |
US20040082182A1 (en) | 2004-04-29 |
KR20010113010A (ko) | 2001-12-24 |
EP1168434B1 (de) | 2007-04-11 |
TW580753B (en) | 2004-03-21 |
SG99903A1 (en) | 2003-11-27 |
US6635566B1 (en) | 2003-10-21 |
JP3637000B2 (ja) | 2005-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |