DE60111302D1 - Laminiertes elektronisches Bauteil, Verfahren zur Herstellung und elektronische Einrichtung - Google Patents

Laminiertes elektronisches Bauteil, Verfahren zur Herstellung und elektronische Einrichtung

Info

Publication number
DE60111302D1
DE60111302D1 DE60111302T DE60111302T DE60111302D1 DE 60111302 D1 DE60111302 D1 DE 60111302D1 DE 60111302 T DE60111302 T DE 60111302T DE 60111302 T DE60111302 T DE 60111302T DE 60111302 D1 DE60111302 D1 DE 60111302D1
Authority
DE
Germany
Prior art keywords
manufacturing
electronic device
electronic component
laminated
laminated electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60111302T
Other languages
English (en)
Other versions
DE60111302T2 (de
Inventor
Norio Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Application granted granted Critical
Publication of DE60111302D1 publication Critical patent/DE60111302D1/de
Publication of DE60111302T2 publication Critical patent/DE60111302T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
DE60111302T 2000-05-22 2001-04-27 Laminiertes elektronisches Bauteil, Verfahren zur Herstellung und elektronische Einrichtung Expired - Lifetime DE60111302T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000149327 2000-05-22
JP2000149327A JP2001332859A (ja) 2000-05-22 2000-05-22 積層型セラミック電子部品およびその製造方法ならびに電子装置

Publications (2)

Publication Number Publication Date
DE60111302D1 true DE60111302D1 (de) 2005-07-14
DE60111302T2 DE60111302T2 (de) 2006-05-11

Family

ID=18655199

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60111302T Expired - Lifetime DE60111302T2 (de) 2000-05-22 2001-04-27 Laminiertes elektronisches Bauteil, Verfahren zur Herstellung und elektronische Einrichtung

Country Status (4)

Country Link
US (1) US6974916B2 (de)
EP (1) EP1158844B1 (de)
JP (1) JP2001332859A (de)
DE (1) DE60111302T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1324402C (zh) 2001-10-30 2007-07-04 钟渊化学工业株式会社 感光性树脂组合物、使用该组合物的感光性薄膜及层压体
US6818985B1 (en) * 2001-12-22 2004-11-16 Skyworks Solutions, Inc. Embedded antenna and semiconductor die on a substrate in a laminate package
TWI237120B (en) * 2002-10-09 2005-08-01 Advanced Semiconductor Eng Impedance standard substrate and method for calibrating vector network analyzer
CN100468706C (zh) * 2003-12-04 2009-03-11 松下电器产业株式会社 电路基板及其制造方法、半导体封装及部件内置模块
US7323887B2 (en) * 2005-04-01 2008-01-29 Rosemount Analytical Inc. Conductivity sensor and manufacturing method therefor
US20080297179A1 (en) * 2007-05-29 2008-12-04 Chang-Dong Feng Multilayer manufacturing for conductivity sensor
JP5201983B2 (ja) * 2007-12-28 2013-06-05 富士通株式会社 電子部品
JP5133047B2 (ja) * 2007-12-28 2013-01-30 太陽誘電株式会社 電子部品の製造方法
US8946904B2 (en) * 2010-08-27 2015-02-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Substrate vias for heat removal from semiconductor die
WO2017130462A1 (ja) * 2016-01-27 2017-08-03 株式会社村田製作所 インダクタ部品およびその製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3968193A (en) * 1971-08-27 1976-07-06 International Business Machines Corporation Firing process for forming a multilayer glass-metal module
US3922479A (en) * 1971-09-15 1975-11-25 Bunker Ramo Coaxial circuit construction and method of making
US4739448A (en) * 1984-06-25 1988-04-19 Magnavox Government And Industrial Electronics Company Microwave multiport multilayered integrated circuit chip carrier
JPS61148847A (ja) 1984-12-21 1986-07-07 Fujitsu Ltd 半導体装置
JPH088417B2 (ja) 1988-11-17 1996-01-29 イビデン株式会社 多層プリント配線板
JPH02148889A (ja) 1988-11-30 1990-06-07 Toshiba Corp セラミックス多層基板
US5061824A (en) * 1989-08-23 1991-10-29 Ncr Corporation Backpanel having multiple logic family signal layers
JP2739726B2 (ja) * 1990-09-27 1998-04-15 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層プリント回路板
JP2996510B2 (ja) * 1990-11-30 2000-01-11 株式会社日立製作所 電子回路基板
JPH06268369A (ja) 1993-03-10 1994-09-22 Asahi Glass Co Ltd ビアホールの充填方法
US5408053A (en) * 1993-11-30 1995-04-18 Hughes Aircraft Company Layered planar transmission lines
JP2715911B2 (ja) 1994-07-06 1998-02-18 日本電気株式会社 多層配線セラミック基板及びその製造方法
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
DE69535391T2 (de) * 1994-08-19 2007-10-31 Hitachi, Ltd. Mehrlagenschaltungssubstrat
US5719749A (en) * 1994-09-26 1998-02-17 Sheldahl, Inc. Printed circuit assembly with fine pitch flexible printed circuit overlay mounted to printed circuit board
EP0804806A1 (de) * 1994-12-22 1997-11-05 Benedict G. Pace Invertiertes chip modul hoher packungsdichte
DE19681758B4 (de) * 1996-06-14 2006-09-14 Ibiden Co., Ltd. Einseitiges Schaltkreissubstrat für mehrlagige Schaltkreisplatine, mehrlagige Schaltkreisplatine und Verfahren zur Herstellung selbiger
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法

Also Published As

Publication number Publication date
DE60111302T2 (de) 2006-05-11
EP1158844A3 (de) 2003-10-15
EP1158844B1 (de) 2005-06-08
US6974916B2 (en) 2005-12-13
JP2001332859A (ja) 2001-11-30
EP1158844A2 (de) 2001-11-28
US20030030985A1 (en) 2003-02-13

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