DE60036305D1 - Selbstjustierte metalldeckschichten für zwischenschicht-metallverbindungen - Google Patents

Selbstjustierte metalldeckschichten für zwischenschicht-metallverbindungen

Info

Publication number
DE60036305D1
DE60036305D1 DE60036305T DE60036305T DE60036305D1 DE 60036305 D1 DE60036305 D1 DE 60036305D1 DE 60036305 T DE60036305 T DE 60036305T DE 60036305 T DE60036305 T DE 60036305T DE 60036305 D1 DE60036305 D1 DE 60036305D1
Authority
DE
Germany
Prior art keywords
self
intermediate layer
metal
adjusted
coverings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60036305T
Other languages
English (en)
Other versions
DE60036305T2 (de
Inventor
Dirk Tobben
Jeffrey Gambino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Qimonda North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Publication of DE60036305D1 publication Critical patent/DE60036305D1/de
Application granted granted Critical
Publication of DE60036305T2 publication Critical patent/DE60036305T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60036305T 1999-10-18 2000-10-04 Selbstjustierte metalldeckschichten für zwischenschicht-metallverbindungen Expired - Lifetime DE60036305T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US420402 1999-10-18
US09/420,402 US6261950B1 (en) 1999-10-18 1999-10-18 Self-aligned metal caps for interlevel metal connections
PCT/US2000/027339 WO2001029892A1 (en) 1999-10-18 2000-10-04 Self-aligned metal caps for interlevel metal connections

Publications (2)

Publication Number Publication Date
DE60036305D1 true DE60036305D1 (de) 2007-10-18
DE60036305T2 DE60036305T2 (de) 2008-05-15

Family

ID=23666322

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60036305T Expired - Lifetime DE60036305T2 (de) 1999-10-18 2000-10-04 Selbstjustierte metalldeckschichten für zwischenschicht-metallverbindungen

Country Status (7)

Country Link
US (1) US6261950B1 (de)
EP (1) EP1230678B1 (de)
JP (1) JP2003527743A (de)
KR (1) KR100468069B1 (de)
DE (1) DE60036305T2 (de)
TW (1) TW465037B (de)
WO (1) WO2001029892A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4190118B2 (ja) * 1999-12-17 2008-12-03 三菱電機株式会社 半導体装置、液晶表示装置および半導体装置の製造方法
US6613671B1 (en) * 2000-03-03 2003-09-02 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
JP2001319928A (ja) * 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
US20050026412A1 (en) * 2000-06-16 2005-02-03 Drynan John M. Interconnect line selectively isolated from an underlying contact plug
US6406996B1 (en) * 2000-09-30 2002-06-18 Advanced Micro Devices, Inc. Sub-cap and method of manufacture therefor in integrated circuit capping layers
US9139906B2 (en) 2001-03-06 2015-09-22 Asm America, Inc. Doping with ALD technology
US7087997B2 (en) * 2001-03-12 2006-08-08 International Business Machines Corporation Copper to aluminum interlayer interconnect using stud and via liner
JP3874268B2 (ja) * 2002-07-24 2007-01-31 Ｔｄｋ株式会社 パターン化薄膜およびその形成方法
US7727892B2 (en) * 2002-09-25 2010-06-01 Intel Corporation Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
US7045406B2 (en) 2002-12-03 2006-05-16 Asm International, N.V. Method of forming an electrode with adjusted work function
US7122414B2 (en) 2002-12-03 2006-10-17 Asm International, Inc. Method to fabricate dual metal CMOS devices
US6955984B2 (en) * 2003-05-16 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment of metal interconnect lines
JP2004349609A (ja) * 2003-05-26 2004-12-09 Renesas Technology Corp 半導体装置およびその製造方法
JP2009524233A (ja) * 2006-01-18 2009-06-25 コニンクレイケ フィリップス エレクトロニクス ナームロゼ フェンノートシャップ 金属線間で自己整合されたトレンチの集積化
KR101427142B1 (ko) 2006-10-05 2014-08-07 에이에스엠 아메리카, 인코포레이티드 금속 규산염 막의 원자층 증착
WO2010016958A1 (en) * 2008-08-07 2010-02-11 International Business Machines Corporation Interconnect structure with metal cap self-aligned to a surface of an embedded conductive material
DE102008042107A1 (de) * 2008-09-15 2010-03-18 Robert Bosch Gmbh Elektronisches Bauteil sowie Verfahren zu seiner Herstellung
US8557702B2 (en) 2009-02-02 2013-10-15 Asm America, Inc. Plasma-enhanced atomic layers deposition of conductive material over dielectric layers
US10177031B2 (en) 2014-12-23 2019-01-08 International Business Machines Corporation Subtractive etch interconnects
US9431292B1 (en) 2015-04-29 2016-08-30 Globalfoundries Inc. Alternate dual damascene method for forming interconnects
US9722038B2 (en) 2015-09-11 2017-08-01 International Business Machines Corporation Metal cap protection layer for gate and contact metallization
US10727111B2 (en) * 2017-07-18 2020-07-28 Taiwan Semiconductor Manufaturing Co., Ltd. Interconnect structure
KR102396806B1 (ko) 2017-08-31 2022-05-12 마이크론 테크놀로지, 인크 반도체 장치, 하이브리드 트랜지스터 및 관련 방법
JP7124059B2 (ja) * 2017-08-31 2022-08-23 マイクロン テクノロジー，インク． 半導体デバイス、トランジスタ、および金属酸化物半導体デバイスを接触させるための関連する方法
US10985076B2 (en) 2018-08-24 2021-04-20 International Business Machines Corporation Single metallization scheme for gate, source, and drain contact integration
US11171051B1 (en) 2020-05-06 2021-11-09 International Business Machines Corporation Contacts and liners having multi-segmented protective caps

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319222A (ja) * 1989-06-15 1991-01-28 Matsushita Electron Corp 半導体装置の製造方法
JP2921773B2 (ja) * 1991-04-05 1999-07-19 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
US5305519A (en) * 1991-10-24 1994-04-26 Kawasaki Steel Corporation Multilevel interconnect structure and method of manufacturing the same
JPH0629399A (ja) * 1992-07-09 1994-02-04 Toshiba Corp 半導体装置の製造方法
US5380546A (en) * 1993-06-09 1995-01-10 Microelectronics And Computer Technology Corporation Multilevel metallization process for electronic components
JP3219909B2 (ja) * 1993-07-09 2001-10-15 株式会社東芝 半導体装置の製造方法
JPH07135188A (ja) * 1993-11-11 1995-05-23 Toshiba Corp 半導体装置の製造方法
EP1098366A1 (de) * 1994-12-29 2001-05-09 STMicroelectronics, Inc. Halbleiterverbindungsstruktur und Verfahren
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US6066558A (en) * 1996-03-05 2000-05-23 Tokyo Electron Limited Multilevel interconnection forming method for forming a semiconductor device
JP3304754B2 (ja) * 1996-04-11 2002-07-22 三菱電機株式会社 集積回路の多段埋め込み配線構造
JP3309717B2 (ja) * 1996-06-26 2002-07-29 三菱電機株式会社 集積回路の配線の製造方法
JPH10135153A (ja) * 1996-10-29 1998-05-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH10144685A (ja) * 1996-11-13 1998-05-29 Sony Corp 半導体装置における配線構造及び配線形成方法

Also Published As

Publication number Publication date
EP1230678B1 (de) 2007-09-05
WO2001029892A1 (en) 2001-04-26
KR20020047242A (ko) 2002-06-21
JP2003527743A (ja) 2003-09-16
TW465037B (en) 2001-11-21
KR100468069B1 (ko) 2005-01-25
EP1230678A1 (de) 2002-08-14
US6261950B1 (en) 2001-07-17
DE60036305T2 (de) 2008-05-15

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA NORTH AMERICA CORP., CARY, N.C., US

8364 No opposition during term of opposition