DE60024393D1 - PLL-Schaltung mit reduziertem Phasenoffset ohne Erhöhung der Betriebsspannung - Google Patents

PLL-Schaltung mit reduziertem Phasenoffset ohne Erhöhung der Betriebsspannung

Info

Publication number
DE60024393D1
DE60024393D1 DE60024393T DE60024393T DE60024393D1 DE 60024393 D1 DE60024393 D1 DE 60024393D1 DE 60024393 T DE60024393 T DE 60024393T DE 60024393 T DE60024393 T DE 60024393T DE 60024393 D1 DE60024393 D1 DE 60024393D1
Authority
DE
Germany
Prior art keywords
increasing
operating voltage
pll circuit
phase offset
reduced phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60024393T
Other languages
English (en)
Other versions
DE60024393T2 (de
Inventor
Susumu Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE60024393D1 publication Critical patent/DE60024393D1/de
Application granted granted Critical
Publication of DE60024393T2 publication Critical patent/DE60024393T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
DE60024393T 1999-10-19 2000-10-13 PLL-Schaltung mit reduziertem Phasenoffset ohne Erhöhung der Betriebsspannung Expired - Fee Related DE60024393T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29637699A JP3356136B2 (ja) 1999-10-19 1999-10-19 Ｐｌｌ回路
JP29637699 1999-10-19

Publications (2)

Publication Number Publication Date
DE60024393D1 true DE60024393D1 (de) 2006-01-05
DE60024393T2 DE60024393T2 (de) 2006-08-24

Family

ID=17832759

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60024393T Expired - Fee Related DE60024393T2 (de) 1999-10-19 2000-10-13 PLL-Schaltung mit reduziertem Phasenoffset ohne Erhöhung der Betriebsspannung

Country Status (6)

Country Link
US (1) US6320435B1 (de)
EP (1) EP1094609B1 (de)
JP (1) JP3356136B2 (de)
KR (1) KR100348198B1 (de)
CN (1) CN1179483C (de)
DE (1) DE60024393T2 (de)

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US7019571B2 (en) * 2004-03-31 2006-03-28 Silicon Laboratories, Inc. Frequency synthesizer for a wireless communication system
DE102004019652A1 (de) * 2004-04-22 2005-11-17 Infineon Technologies Ag Fehlerkompensierte Ladungspumpen-Schaltung und Verfahren zur Erzeugung eines fehlerkompensierten Ausgangsstroms einer Ladungspumpen-Schaltung
US7002418B2 (en) * 2004-05-07 2006-02-21 Lattice Semiconductor Corporation Control signal generation for a low jitter switched-capacitor frequency synthesizer
US7176731B2 (en) * 2004-08-26 2007-02-13 International Business Machines Corporation Variation tolerant charge leakage correction circuit for phase locked loops
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US7777541B1 (en) 2006-02-01 2010-08-17 Cypress Semiconductor Corporation Charge pump circuit and method for phase locked loop
JP4668868B2 (ja) * 2006-08-21 2011-04-13 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
JP4769694B2 (ja) * 2006-11-20 2011-09-07 富士通テン株式会社 電圧出力回路，集積回路，および電子機器
US8334725B2 (en) * 2007-04-11 2012-12-18 Mediatek Inc. Circuit and method for controlling mixed mode controlled oscillator and CDR circuit using the same
US20090002038A1 (en) * 2007-06-29 2009-01-01 Boerstler David W Phase Locked Loop with Stabilized Dynamic Response
US7958469B2 (en) * 2007-06-29 2011-06-07 International Business Machines Corporation Design structure for a phase locked loop with stabilized dynamic response
JP2009152734A (ja) * 2007-12-19 2009-07-09 Seiko Instruments Inc Ｐｌｌ回路
US8169241B2 (en) 2008-01-15 2012-05-01 Atmel Rousset S.A.S. Proportional phase comparator and method for phase-aligning digital signals
US7741919B2 (en) * 2008-05-02 2010-06-22 International Business Machines Corporation Architecture for maintaining constant voltage-controlled oscillator gain
CN101944910B (zh) * 2009-07-07 2017-03-22 晨星软件研发(深圳)有限公司 双锁相环电路及其控制方法
TWI381646B (zh) * 2009-10-01 2013-01-01 Mstar Semiconductor Inc 鎖相迴路之迴路頻寬控制裝置及迴路頻寬控制方法
KR101283468B1 (ko) * 2009-11-19 2013-07-23 한국전자통신연구원 루프필터 및 이를 포함하는 위상 고정 루프
CN102859879B (zh) 2010-05-13 2015-03-11 华为技术有限公司 用于校验锁相环中的输出频率的系统和方法
JP5738749B2 (ja) * 2011-12-15 2015-06-24 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
US9065457B2 (en) * 2012-04-26 2015-06-23 Skyworks Solutions, Inc. Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis
JP6559548B2 (ja) * 2015-11-11 2019-08-14 エイブリック株式会社 発振回路装置
DK3396833T3 (da) * 2017-04-28 2019-11-18 Gn Hearing As Høreindretning, der omfatter switched capacitor-dc-dc-omformer med lav elektromagnetisk emission
JP7388240B2 (ja) 2020-02-27 2023-11-29 セイコーエプソン株式会社 チャージポンプ回路、ｐｌｌ回路および発振器

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Also Published As

Publication number Publication date
EP1094609A2 (de) 2001-04-25
JP3356136B2 (ja) 2002-12-09
CN1293489A (zh) 2001-05-02
EP1094609A3 (de) 2002-11-20
KR20010050937A (ko) 2001-06-25
EP1094609B1 (de) 2005-11-30
DE60024393T2 (de) 2006-08-24
CN1179483C (zh) 2004-12-08
JP2001119296A (ja) 2001-04-27
KR100348198B1 (ko) 2002-08-09
US6320435B1 (en) 2001-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee