DE60001095D1 - Serienschalter-treiberarchitektur für eine automatische testeinrichtung - Google Patents

Serienschalter-treiberarchitektur für eine automatische testeinrichtung

Info

Publication number
DE60001095D1
DE60001095D1 DE60001095T DE60001095T DE60001095D1 DE 60001095 D1 DE60001095 D1 DE 60001095D1 DE 60001095 T DE60001095 T DE 60001095T DE 60001095 T DE60001095 T DE 60001095T DE 60001095 D1 DE60001095 D1 DE 60001095D1
Authority
DE
Germany
Prior art keywords
signal level
switching unit
test device
signal
automatic test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60001095T
Other languages
English (en)
Other versions
DE60001095T2 (de
Inventor
Peter Breger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE60001095D1 publication Critical patent/DE60001095D1/de
Publication of DE60001095T2 publication Critical patent/DE60001095T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE60001095T 1999-02-19 2000-02-18 Serienschalter-treiberarchitektur für eine automatische testeinrichtung Expired - Lifetime DE60001095T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/253,175 US6137310A (en) 1999-02-19 1999-02-19 Serial switch driver architecture for automatic test equipment
PCT/US2000/004454 WO2000049715A2 (en) 1999-02-19 2000-02-18 Serial switch driver architecture for automatic test equipment

Publications (2)

Publication Number Publication Date
DE60001095D1 true DE60001095D1 (de) 2003-02-06
DE60001095T2 DE60001095T2 (de) 2003-11-20

Family

ID=22959186

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60001095T Expired - Lifetime DE60001095T2 (de) 1999-02-19 2000-02-18 Serienschalter-treiberarchitektur für eine automatische testeinrichtung

Country Status (8)

Country Link
US (1) US6137310A (de)
EP (1) EP1145433B1 (de)
JP (1) JP4593791B2 (de)
KR (1) KR100668250B1 (de)
DE (1) DE60001095T2 (de)
MY (1) MY120264A (de)
TW (1) TW444251B (de)
WO (1) WO2000049715A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279953B2 (en) * 2004-09-21 2007-10-09 Analog Devices, Inc. Current switch and method of driving the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4029971A (en) * 1976-02-13 1977-06-14 Rca Corporation Tri-state logic circuit
US4363978A (en) * 1980-07-31 1982-12-14 Rockwell International Corporation Reduced power tristate driver circuit
JPS5873881A (ja) * 1981-10-29 1983-05-04 Advantest Corp Ｉｃテスタ
US4572971A (en) * 1983-03-25 1986-02-25 Fairchild Camera And Instrument Corporation Tri-state driver circuit for automatic test equipment
US4737663A (en) * 1984-03-01 1988-04-12 Advanced Micro Devices, Inc. Current source arrangement for three-level emitter-coupled logic and four-level current mode logic
US4998026A (en) * 1989-04-19 1991-03-05 Hewlett-Packard Company Driver circuit for in-circuit overdrive/functional tester
JPH03277983A (ja) * 1990-03-28 1991-12-09 Ando Electric Co Ltd Ｄｂ型ａｓによるｄｕｔ負荷切換回路
US5159216A (en) * 1990-10-25 1992-10-27 Triquint Semiconductor, Inc. Precision tristate output driver circuit having a voltage clamping feature
JP2866750B2 (ja) * 1991-01-28 1999-03-08 三菱電機株式会社 半導体試験装置および半導体装置の試験方法
US5146159A (en) * 1991-02-01 1992-09-08 Schlumberger Technologies, Inc. Pin driver for in-circuit test apparatus
US5146161A (en) * 1991-04-05 1992-09-08 Vlsi Technology, Inc. Integrated circuit test system
US5250860A (en) * 1992-06-25 1993-10-05 International Business Machines Corporation Three-level cascode differential current switch
US5323068A (en) * 1992-11-17 1994-06-21 National Semiconductor Corporation Low power low temperature ECL output driver circuit
US5500817A (en) * 1993-01-21 1996-03-19 Micron Technology, Inc. True tristate output buffer and a method for driving a potential of an output pad to three distinct conditions
DE69426713T2 (de) * 1993-06-16 2001-09-06 Koninkl Philips Electronics Nv Integrierte Logikschaltung mit Logikgattern mit einem einzigen Eingang
JP3539509B2 (ja) * 1994-03-15 2004-07-07 株式会社ルネサステクノロジ 電流切換型論理回路
US5656953A (en) * 1995-05-31 1997-08-12 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5578941A (en) * 1995-08-23 1996-11-26 Micron Technology, Inc. Voltage compensating CMOS input buffer circuit
US5644258A (en) * 1996-01-04 1997-07-01 Winbond Electronics Corp. Driver circuit, with low idle power consumption, for an attachment unit interface
JP3734877B2 (ja) * 1996-03-22 2006-01-11 株式会社アドバンテスト Ｉｃ試験装置のｉ／ｏ切換スイッチ回路
US5714892A (en) * 1996-04-04 1998-02-03 Analog Devices, Inc. Three state logic input
US5900744A (en) * 1996-12-30 1999-05-04 Intel Corporation Method and apparatus for providing a high speed tristate buffer
JP3599988B2 (ja) * 1997-12-09 2004-12-08 日立ハイテク電子エンジニアリング株式会社 電子デバイスへの負荷電流出力回路およびｉｃテスタ

Also Published As

Publication number Publication date
JP2002537708A (ja) 2002-11-05
KR100668250B1 (ko) 2007-01-12
MY120264A (en) 2005-09-30
KR20010110440A (ko) 2001-12-13
WO2000049715A2 (en) 2000-08-24
EP1145433A2 (de) 2001-10-17
US6137310A (en) 2000-10-24
JP4593791B2 (ja) 2010-12-08
EP1145433B1 (de) 2003-01-02
WO2000049715A3 (en) 2001-02-15
TW444251B (en) 2001-07-01
DE60001095T2 (de) 2003-11-20

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Legal Events

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