ATE376189T1 - Elektronischer schaltkreis und testverfahren - Google Patents

Elektronischer schaltkreis und testverfahren

Info

Publication number
ATE376189T1
ATE376189T1 AT02749176T AT02749176T ATE376189T1 AT E376189 T1 ATE376189 T1 AT E376189T1 AT 02749176 T AT02749176 T AT 02749176T AT 02749176 T AT02749176 T AT 02749176T AT E376189 T1 ATE376189 T1 AT E376189T1
Authority
AT
Austria
Prior art keywords
contacts
input
contact
output
redefinable
Prior art date
Application number
AT02749176T
Other languages
English (en)
Inventor
Alexander Biewenga
De Logt Leon Van
Jong Franciscus De
Guillaume Lousberg
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE376189T1 publication Critical patent/ATE376189T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G11C2029/3602—Pattern generator

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Filters And Equalizers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Electric Clocks (AREA)
AT02749176T 2001-08-16 2002-07-09 Elektronischer schaltkreis und testverfahren ATE376189T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01203126 2001-08-16

Publications (1)

Publication Number Publication Date
ATE376189T1 true ATE376189T1 (de) 2007-11-15

Family

ID=8180805

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02749176T ATE376189T1 (de) 2001-08-16 2002-07-09 Elektronischer schaltkreis und testverfahren

Country Status (9)

Country Link
US (1) US6883129B2 (de)
EP (1) EP1417502B1 (de)
JP (1) JP3992683B2 (de)
KR (1) KR100906513B1 (de)
CN (1) CN100371727C (de)
AT (1) ATE376189T1 (de)
DE (1) DE60223043T2 (de)
TW (1) TWI223094B (de)
WO (1) WO2003016922A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6971045B1 (en) * 2002-05-20 2005-11-29 Cyress Semiconductor Corp. Reducing tester channels for high pinout integrated circuits
JP3901151B2 (ja) * 2003-12-25 2007-04-04 セイコーエプソン株式会社 ドライバｉｃ並びにドライバｉｃ及び出力装置の検査方法
US7685483B1 (en) * 2005-06-20 2010-03-23 Lattice Semiconductor Corporation Design features for testing integrated circuits
CN100417098C (zh) * 2005-08-04 2008-09-03 上海华为技术有限公司 E1/t1连接错误检测方法
DE102010002460A1 (de) * 2010-03-01 2011-09-01 Robert Bosch Gmbh Verfahren zum Testen eines integrierten Schaltkreises
FR3051285B1 (fr) * 2016-05-13 2018-05-18 Zodiac Aerotechnics Circuit electronique a fonctions modifiables

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4658225A (en) * 1984-07-05 1987-04-14 Hewlett-Packard Company Amplitude insensitive delay lines in a transversal filter
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
EP0358376B1 (de) 1988-09-07 1995-02-22 Texas Instruments Incorporated Integrierte Prüfschaltung
US5392297A (en) * 1989-04-18 1995-02-21 Vlsi Technology, Inc. Method for automatic isolation of functional blocks within integrated circuits
US5155733A (en) * 1990-12-26 1992-10-13 Ag Communication Systems Corporation Arrangement for testing digital circuit devices having bidirectional outputs
US5481471A (en) * 1992-12-18 1996-01-02 Hughes Aircraft Company Mixed signal integrated circuit architecture and test methodology
TW307927B (de) * 1994-08-29 1997-06-11 Matsushita Electric Industrial Co Ltd
JPH08147110A (ja) * 1994-11-18 1996-06-07 Sony Corp データ記録媒体管理方法、データ記録媒体管理装置およびデータ記録媒体
JP3673027B2 (ja) 1996-09-05 2005-07-20 沖電気工業株式会社 テスト対象の半導体記憶回路を備えた半導体記憶装置
US6087968A (en) * 1997-04-16 2000-07-11 U.S. Philips Corporation Analog to digital converter comprising an asynchronous sigma delta modulator and decimating digital filter
JP2001520780A (ja) 1998-02-02 2001-10-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 相互接続部テストユニットを有する回路及び第１電子回路と第２電子回路との間の相互接続部をテストする方法
US6378090B1 (en) 1998-04-24 2002-04-23 Texas Instruments Incorporated Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port
US6499125B1 (en) * 1998-11-24 2002-12-24 Matsushita Electric Industrial Co., Ltd. Method for inserting test circuit and method for converting test data
US6456961B1 (en) * 1999-04-30 2002-09-24 Srinivas Patil Method and apparatus for creating testable circuit designs having embedded cores
DE10066260B4 (de) 1999-04-30 2013-11-14 Fujitsu Semiconductor Ltd. Halbleiter-Speicheranordnung, Leiterplatte, auf welcher eine Halbleiter-Speicheranordnung montiert ist, und Verfahren zum Testen der Zwischenverbindung zwischen einer Halbleiter-Speicheranordnung und einer Leiterplatte
JP3483130B2 (ja) * 1999-11-29 2004-01-06 松下電器産業株式会社 集積回路の検査方法

Also Published As

Publication number Publication date
JP3992683B2 (ja) 2007-10-17
CN100371727C (zh) 2008-02-27
EP1417502A2 (de) 2004-05-12
KR100906513B1 (ko) 2009-07-07
DE60223043T2 (de) 2008-07-24
TWI223094B (en) 2004-11-01
KR20040027889A (ko) 2004-04-01
WO2003016922A3 (en) 2003-05-30
WO2003016922A2 (en) 2003-02-27
EP1417502B1 (de) 2007-10-17
CN1541336A (zh) 2004-10-27
JP2005500536A (ja) 2005-01-06
US20030051198A1 (en) 2003-03-13
DE60223043D1 (de) 2007-11-29
US6883129B2 (en) 2005-04-19

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties