DE602005014261D1 - Schaltungsverbindungs-prüfanordnung und ansatz dafür - Google Patents

Schaltungsverbindungs-prüfanordnung und ansatz dafür

Info

Publication number
DE602005014261D1
DE602005014261D1 DE602005014261T DE602005014261T DE602005014261D1 DE 602005014261 D1 DE602005014261 D1 DE 602005014261D1 DE 602005014261 T DE602005014261 T DE 602005014261T DE 602005014261 T DE602005014261 T DE 602005014261T DE 602005014261 D1 DE602005014261 D1 DE 602005014261D1
Authority
DE
Germany
Prior art keywords
logic level
flip
reset
flop
approach
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005014261T
Other languages
English (en)
Inventor
Rodger Franks Schuttert
Tom Waayers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602005014261D1 publication Critical patent/DE602005014261D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
DE602005014261T 2004-07-28 2005-07-28 Schaltungsverbindungs-prüfanordnung und ansatz dafür Active DE602005014261D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59183404P 2004-07-28 2004-07-28
PCT/IB2005/052551 WO2007026191A1 (en) 2004-07-28 2005-07-28 Circuit interconnect testing arrangement and approach therefor

Publications (1)

Publication Number Publication Date
DE602005014261D1 true DE602005014261D1 (de) 2009-06-10

Family

ID=35058790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005014261T Active DE602005014261D1 (de) 2004-07-28 2005-07-28 Schaltungsverbindungs-prüfanordnung und ansatz dafür

Country Status (7)

Country Link
US (1) US7685488B2 (de)
EP (1) EP1810044B1 (de)
JP (1) JP2008508541A (de)
CN (1) CN101031809B (de)
AT (1) ATE430319T1 (de)
DE (1) DE602005014261D1 (de)
WO (1) WO2007026191A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8531197B2 (en) * 2008-07-17 2013-09-10 Freescale Semiconductor, Inc. Integrated circuit die, an integrated circuit package and a method for connecting an integrated circuit die to an external device
EP2331979B1 (de) * 2008-09-26 2012-07-04 Nxp B.V. Verfahren zur prüfung einer teilweise zusammengebauten mehrchipanordnung, integrierter schaltungschip und mehrchipanordnung
US7945831B2 (en) * 2008-10-31 2011-05-17 Texas Instruments Incorporated Gating TDO from plural JTAG circuits
CN103091626B (zh) * 2011-11-04 2015-07-15 深圳迈瑞生物医疗电子股份有限公司 Jtag测试链路及其超声诊断仪
US10473717B2 (en) * 2016-11-09 2019-11-12 Texas Instruments Incorporated Methods and apparatus for test insertion points

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056094A (en) * 1989-06-09 1991-10-08 Texas Instruments Incorporated Delay fault testing method and apparatus
US5815512A (en) * 1994-05-26 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device
US6000051A (en) * 1997-10-10 1999-12-07 Logic Vision, Inc. Method and apparatus for high-speed interconnect testing
FR2790832B1 (fr) 1999-03-08 2001-06-08 France Telecom Procede de test de circuits integres avec acces a des points de memorisation du circuit
GB2370364B (en) * 2000-12-22 2004-06-30 Advanced Risc Mach Ltd Testing integrated circuits
EP1233276B1 (de) * 2001-02-19 2004-12-01 Lucent Technologies Inc. Abtastverzögerungskette zur Verzögerungsmessung
CN1369714A (zh) * 2001-07-18 2002-09-18 中国人民解放军第二炮兵工程学院技术开发中心 大规模集成电路边界扫描测试系统
EP1286170A1 (de) * 2001-08-14 2003-02-26 Lucent Technologies Inc. Flipflop für "Boundary-Scan" mit Bypass für die Speicherzelle des Flipflops
US20030149924A1 (en) * 2002-02-01 2003-08-07 Bedal Glenn E. Method and apparatus for detecting faults on integrated circuits
WO2004068156A1 (en) 2003-01-28 2004-08-12 Koninklijke Philips Electronics N.V. Boundary scan circuit with integrated sensor for sensing physical operating parameters
US7305601B2 (en) * 2004-11-17 2007-12-04 Lsi Corporation Method and test apparatus for testing integrated circuits using both valid and invalid test data

Also Published As

Publication number Publication date
US7685488B2 (en) 2010-03-23
CN101031809A (zh) 2007-09-05
CN101031809B (zh) 2012-08-01
US20090077438A1 (en) 2009-03-19
WO2007026191A1 (en) 2007-03-08
EP1810044A1 (de) 2007-07-25
EP1810044B1 (de) 2009-04-29
JP2008508541A (ja) 2008-03-21
ATE430319T1 (de) 2009-05-15

Similar Documents

Publication Publication Date Title
DE602005014261D1 (de) Schaltungsverbindungs-prüfanordnung und ansatz dafür
TW200717002A (en) Electronic device having and interface supported testing mode
DE60212962D1 (de) Hierarchischer intergrierterselbsttest
ATE427584T1 (de) Hochleitstungs-flip-flop mit doppeltem gatter
TW200626917A (en) Low cost test for IC's or electrical modules using standard reconfigurable logic devices
DE60203032D1 (de) Integrierte Halbleiterschaltung
MY136254A (en) Latch circuit including a data retention latch
US10451674B2 (en) Apparatus and method for at-speed scan test
TW200706891A (en) Semiconductor integrated circuit and method for testing connection state between semiconductor integrated circuits
CN105158674B (zh) 利用寄生效应的硬件木马检测方法和系统
TW200636668A (en) Level shift circuit, electro-optical device using the same, and electronic apparatus
DE59909951D1 (de) Schaltungsanordnung mit temperaturabhängiger Halbleiterbauelement-Test- und Reparaturlogik
KR102577213B1 (ko) 집적 회로에서의 동적 스캔 체인 재구성
TW200628806A (en) A device with a sensor arrangement
DE50113590D1 (de) Leiterplattenanordnung
WO2003027696A3 (de) Elektronischer baustein und verfahren zu dessen qualifizierungsmessung
DE60223043D1 (de) Elektronischer schaltkreis und testverfahren
WO2003027697A3 (de) Elektronischer baustein
CN207408892U (zh) 一种基于飞腾平台的指纹识别装置及台式机
TW200633381A (en) Integrated circuit for reducing use of pins and setting configuration data
CN205645799U (zh) 一种插拔式引脚结构、可插拔的按键开关及键盘
EP1263139A3 (de) Störimpulsfreier Multiplexer
CN105549707B (zh) 一种防止设备开机失败的复位电路及复位方法
KR940018754A (ko) 버스 사이징(sizing) 기능을 갖는 마이크로프로세서
CN203365631U (zh) 一种jtag电路

Legal Events

Date Code Title Description
8364 No opposition during term of opposition