ATE464570T1 - Testen einer integrierten schaltung mit mehreren taktdomänen - Google Patents

Testen einer integrierten schaltung mit mehreren taktdomänen

Info

Publication number
ATE464570T1
ATE464570T1 AT06710860T AT06710860T ATE464570T1 AT E464570 T1 ATE464570 T1 AT E464570T1 AT 06710860 T AT06710860 T AT 06710860T AT 06710860 T AT06710860 T AT 06710860T AT E464570 T1 ATE464570 T1 AT E464570T1
Authority
AT
Austria
Prior art keywords
test
integrated circuit
clock domain
testing
functional
Prior art date
Application number
AT06710860T
Other languages
English (en)
Inventor
Thomas F Waayers
Richard Morren
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE464570T1 publication Critical patent/ATE464570T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Peptides Or Proteins (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Chemical And Physical Treatments For Wood And The Like (AREA)
AT06710860T 2005-02-11 2006-02-09 Testen einer integrierten schaltung mit mehreren taktdomänen ATE464570T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05101041 2005-02-11
PCT/IB2006/050421 WO2006085276A1 (en) 2005-02-11 2006-02-09 Testing of an integrated circuit with a plurality of clock domains

Publications (1)

Publication Number Publication Date
ATE464570T1 true ATE464570T1 (de) 2010-04-15

Family

ID=36579382

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06710860T ATE464570T1 (de) 2005-02-11 2006-02-09 Testen einer integrierten schaltung mit mehreren taktdomänen

Country Status (7)

Country Link
US (1) US8410787B2 (de)
EP (1) EP1851560B1 (de)
JP (1) JP2008530549A (de)
CN (1) CN101156076B (de)
AT (1) ATE464570T1 (de)
DE (1) DE602006013600D1 (de)
WO (1) WO2006085276A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512363B (zh) * 2006-08-31 2012-07-25 Nxp股份有限公司 多时钟片基系统和电子设备
JP2010091482A (ja) * 2008-10-09 2010-04-22 Toshiba Corp 半導体集積回路装置及びその遅延故障テスト方法
US7996739B2 (en) * 2009-09-11 2011-08-09 International Business Machines Corporation Avoiding race conditions at clock domain crossings in an edge based scan design
TWI416147B (zh) * 2011-03-09 2013-11-21 Global Unichip Corp 於積體電路設計中進行測試時脈域設計的方法及相關的電腦可讀媒體
US8812921B2 (en) 2011-10-25 2014-08-19 Lsi Corporation Dynamic clock domain bypass for scan chains
US8850280B2 (en) * 2011-10-28 2014-09-30 Lsi Corporation Scan enable timing control for testing of scan cells
US8645778B2 (en) 2011-12-31 2014-02-04 Lsi Corporation Scan test circuitry with delay defect bypass functionality
US8726108B2 (en) 2012-01-12 2014-05-13 Lsi Corporation Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
JP6424271B2 (ja) 2015-04-16 2018-11-14 ルネサスエレクトロニクス株式会社 半導体装置
US10060971B2 (en) * 2016-08-16 2018-08-28 International Business Machines Corporation Adjusting latency in a scan cell
US10502784B2 (en) * 2017-09-22 2019-12-10 Stmicroelectronics International N.V. Voltage level monitoring of an integrated circuit for production test and debug
US11422188B2 (en) * 2018-03-22 2022-08-23 Siemens Industry Software Inc Isometric control data generation for test compression

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295284A (ja) * 1988-09-30 1990-04-06 Mitsubishi Electric Corp 半導体集積回路装置
US5909451A (en) * 1996-11-21 1999-06-01 Sun Microsystems, Inc. System and method for providing scan chain for digital electronic device having multiple clock domains
JP3848686B2 (ja) * 1996-12-13 2006-11-22 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 第１および第２クロック領域を具える集積回路と、このような回路を試験する方法
EP0965850A1 (de) 1998-06-17 1999-12-22 Lucent Technologies Inc. Verfahren zum Abtastprüfen für integrierten Schaltkreis mit Mehrfachtaktgeber
JP2000310671A (ja) * 1999-04-28 2000-11-07 Matsushita Electric Ind Co Ltd スキャンフリップフロップ
US6442722B1 (en) 1999-10-29 2002-08-27 Logicvision, Inc. Method and apparatus for testing circuits with multiple clocks
JP4441997B2 (ja) 2000-07-05 2010-03-31 パナソニック株式会社 成形金型
KR100381959B1 (ko) 2000-08-31 2003-05-01 삼성전자주식회사 테스트 포인트가 삽입된 반도체 집적회로 장치
US6957403B2 (en) 2001-03-30 2005-10-18 Syntest Technologies, Inc. Computer-aided design system to automate scan synthesis at register-transfer level
JP2005530172A (ja) * 2002-06-21 2005-10-06 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 非同期的に動作する構成要素を有する電子回路

Also Published As

Publication number Publication date
EP1851560B1 (de) 2010-04-14
WO2006085276A1 (en) 2006-08-17
CN101156076B (zh) 2011-04-27
CN101156076A (zh) 2008-04-02
JP2008530549A (ja) 2008-08-07
US20100188096A1 (en) 2010-07-29
DE602006013600D1 (de) 2010-05-27
EP1851560A1 (de) 2007-11-07
US8410787B2 (en) 2013-04-02

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