ATE468541T1 - Prüfen einer integrierten schaltung, die geheiminformationen enthält - Google Patents

Prüfen einer integrierten schaltung, die geheiminformationen enthält

Info

Publication number
ATE468541T1
ATE468541T1 AT06795621T AT06795621T ATE468541T1 AT E468541 T1 ATE468541 T1 AT E468541T1 AT 06795621 T AT06795621 T AT 06795621T AT 06795621 T AT06795621 T AT 06795621T AT E468541 T1 ATE468541 T1 AT E468541T1
Authority
AT
Austria
Prior art keywords
scan chain
testing
integrated circuit
shift path
secret information
Prior art date
Application number
AT06795621T
Other languages
English (en)
Inventor
Andre Nieuwland
Sandeepkumar Goel
Erik Marinissen
Hubertus Vermeulen
Hendrikus Vranken
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE468541T1 publication Critical patent/ATE468541T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Storage Device Security (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
AT06795621T 2005-08-10 2006-08-09 Prüfen einer integrierten schaltung, die geheiminformationen enthält ATE468541T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05107366 2005-08-10
PCT/IB2006/052748 WO2007017839A2 (en) 2005-08-10 2006-08-09 Testing of an integrated circuit that contains secret information

Publications (1)

Publication Number Publication Date
ATE468541T1 true ATE468541T1 (de) 2010-06-15

Family

ID=37606833

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06795621T ATE468541T1 (de) 2005-08-10 2006-08-09 Prüfen einer integrierten schaltung, die geheiminformationen enthält

Country Status (7)

Country Link
US (1) US8539292B2 (de)
EP (1) EP1917535B1 (de)
JP (1) JP2009505059A (de)
CN (1) CN101238381A (de)
AT (1) ATE468541T1 (de)
DE (1) DE602006014417D1 (de)
WO (1) WO2007017839A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60130743T2 (de) 2000-03-24 2008-07-17 Biosphere Medical, Inc., Rockland Mikrokugeln zur aktiven embolisierung
ES2568782T3 (es) 2005-05-09 2016-05-04 Biosphere Medical, S.A. Composiciones y métodos de uso de microesferas y agentes de contraste no iónicos
CN101238382B (zh) * 2005-08-10 2012-03-28 Nxp股份有限公司 测试包含秘密信息的集成电路的方法
FR2897440A1 (fr) * 2006-02-10 2007-08-17 St Microelectronics Sa Circuit electronique comprenant un mode de test securise par rupture d'une chaine de test, et procede associe.
US8495758B2 (en) * 2010-06-18 2013-07-23 Alcatel Lucent Method and apparatus for providing scan chain security
JP5793978B2 (ja) 2011-06-13 2015-10-14 富士通セミコンダクター株式会社 半導体装置
US8924802B2 (en) * 2011-08-17 2014-12-30 Texas Instruments Incorporated IC TAP with dual port router and additional capture input
CN105378750A (zh) * 2013-03-14 2016-03-02 纽约大学 用于帮助逻辑加密的系统、方法和计算机可访问介质
US20140355658A1 (en) * 2013-05-30 2014-12-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (ACE) For A Receiver
JP6107519B2 (ja) * 2013-07-31 2017-04-05 富士通セミコンダクター株式会社 半導体装置及びその試験方法
CN106556792B (zh) * 2015-09-28 2021-03-19 恩智浦美国有限公司 能够进行安全扫描的集成电路
KR102538258B1 (ko) 2016-07-25 2023-05-31 삼성전자주식회사 데이터 저장 장치 및 이를 포함하는 데이터 처리 시스템
CN106646203B (zh) * 2016-12-16 2019-03-05 北京航空航天大学 防止利用扫描链攻击集成电路芯片的动态混淆扫描链结构
US10168386B2 (en) 2017-01-13 2019-01-01 International Business Machines Corporation Scan chain latency reduction
US10481205B2 (en) 2017-07-27 2019-11-19 Seagate Technology Llc Robust secure testing of integrated circuits
CN110514981B (zh) * 2018-05-22 2022-04-12 龙芯中科技术股份有限公司 集成电路的时钟控制方法、装置及集成电路
CN109581183B (zh) * 2018-10-23 2020-07-10 中国科学院计算技术研究所 一种集成电路的安全测试方法与系统
KR102620784B1 (ko) * 2021-12-28 2024-01-02 연세대학교 산학협력단 보안 스캔 체인 회로 및 스캔 체인 회로 보안 방법
US20230288477A1 (en) * 2022-03-14 2023-09-14 Duke University Dynamic scan obfuscation for integrated circuit protections

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357572A (en) 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
US6260165B1 (en) * 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
EP1089083A1 (de) 1999-09-03 2001-04-04 Sony Corporation Halbleiterschaltung mit Abtastpfadschaltungen
US7171542B1 (en) * 2000-06-19 2007-01-30 Silicon Labs Cp, Inc. Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins
EP1331539B1 (de) * 2002-01-16 2016-09-28 Texas Instruments France Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen
US7185249B2 (en) 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
US7228474B2 (en) * 2003-01-07 2007-06-05 Sun Microsystems, Inc. Semiconductor device and method and apparatus for testing such a device
US6854807B2 (en) 2003-06-27 2005-02-15 Deltess Corporation Lounge chair with closeable face opening
JP2007506088A (ja) * 2003-09-19 2007-03-15 コニンクリユケ フィリップス エレクトロニクス エヌ．ブイ． 秘密サブモジュールを有する電子回路
US7353470B2 (en) * 2005-02-14 2008-04-01 On-Chip Technologies, Inc. Variable clocked scan test improvements
JP5099869B2 (ja) * 2005-02-23 2012-12-19 ルネサスエレクトロニクス株式会社 半導体集積回路および半導体集積回路のテスト方法
US7334173B2 (en) * 2005-06-28 2008-02-19 Transmeta Corporation Method and system for protecting processors from unauthorized debug access

Also Published As

Publication number Publication date
JP2009505059A (ja) 2009-02-05
WO2007017839A2 (en) 2007-02-15
DE602006014417D1 (de) 2010-07-01
CN101238381A (zh) 2008-08-06
EP1917535A2 (de) 2008-05-07
WO2007017839A3 (en) 2007-07-12
EP1917535B1 (de) 2010-05-19
US8539292B2 (en) 2013-09-17
US20100223515A1 (en) 2010-09-02

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Legal Events

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