ATE444555T1 - Festphasentakt und strobe-signale in verketteten chips - Google Patents

Festphasentakt und strobe-signale in verketteten chips

Info

Publication number
ATE444555T1
ATE444555T1 AT04815495T AT04815495T ATE444555T1 AT E444555 T1 ATE444555 T1 AT E444555T1 AT 04815495 T AT04815495 T AT 04815495T AT 04815495 T AT04815495 T AT 04815495T AT E444555 T1 ATE444555 T1 AT E444555T1
Authority
AT
Austria
Prior art keywords
conquered
chips
fixed phase
phase clock
strobe signals
Prior art date
Application number
AT04815495T
Other languages
English (en)
Inventor
Stephen Mooney
Joseph Kennedy
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE444555T1 publication Critical patent/ATE444555T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Electronic Switches (AREA)
AT04815495T 2003-12-30 2004-12-23 Festphasentakt und strobe-signale in verketteten chips ATE444555T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/749,677 US7031221B2 (en) 2003-12-30 2003-12-30 Fixed phase clock and strobe signals in daisy chained chips
PCT/US2004/043426 WO2005066966A1 (en) 2003-12-30 2004-12-23 Fixed phase clock and strobe signals in daisy chained chips

Publications (1)

Publication Number Publication Date
ATE444555T1 true ATE444555T1 (de) 2009-10-15

Family

ID=34711113

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04815495T ATE444555T1 (de) 2003-12-30 2004-12-23 Festphasentakt und strobe-signale in verketteten chips

Country Status (9)

Country Link
US (1) US7031221B2 (de)
EP (1) EP1700308B1 (de)
KR (1) KR100806465B1 (de)
CN (1) CN1890754B (de)
AT (1) ATE444555T1 (de)
DE (1) DE602004023423D1 (de)
HK (1) HK1091941A1 (de)
TW (1) TWI269950B (de)
WO (1) WO2005066966A1 (de)

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Also Published As

Publication number Publication date
TW200525319A (en) 2005-08-01
TWI269950B (en) 2007-01-01
CN1890754A (zh) 2007-01-03
EP1700308B1 (de) 2009-09-30
US7031221B2 (en) 2006-04-18
EP1700308A1 (de) 2006-09-13
KR100806465B1 (ko) 2008-02-21
HK1091941A1 (en) 2007-01-26
CN1890754B (zh) 2010-05-26
WO2005066966A1 (en) 2005-07-21
US20050146980A1 (en) 2005-07-07
DE602004023423D1 (de) 2009-11-12
KR20060101786A (ko) 2006-09-26

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